Kazuhisa Sunaga

An on-chip 96.5% current efficiency CMOS linear regulator

Tetsuo Endoh, Fujio Masuoka, Hiroshi Sakuraba, 2001, ASP-DAC '01.

An 18Gb/s duobinary receiver with a CDR-assisted DFE

Koichi Yamaguchi, Kazumasa Suzuki, Kazuhisa Sunaga, 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

A 16Gb/s 1st-Tap FFE and 3-Tap DFE in 90nm CMOS

Koichi Yamaguchi, Masayuki Mizuno, Kazuhisa Sunaga, 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

A 6Gb/s receiver with discrete-time based channel filtering for wireline FDM communications

Tadahiro Kuroda, Koichi Yamaguchi, Masayuki Mizuno, 2010, IEEE Custom Integrated Circuits Conference 2010.

Oversampled Edge Equalization

Muneo Fukaishi, Makoto Takamiya, Mitsutoshi Sugawara, 2005 .

6 12 Gb / s Duobinary Signaling with × 2 Oversampled Edge Equalization

Muneo Fukaishi, Mitsutoshi Sugawara, Shunichi Kaeriyama, 2009 .