BagherzadehNader

发表

On-chip parallel and network-based systems

Sarbazi-AzadHamid, DaneshtalabMasoud, BagherzadehNader, 2015 .

A load-balanced congestion-aware wireless network-on-chip design for multi-core platforms

BagherzadehNader, WangChifeng, HuWen-Hsiang, 2012 .

System-Level Analysis of 3D ICs with Thermal TSVs

BagherzadehNader, LeeJaeho, AlqahtaniAyed, 2018 .

Analytical Reliability Analysis of 3D NoC under TSV Failure

BagherzadehNader, KhayambashiMisagh, M YaghiniPooria, 2015 .

A high level power model for Network-on-Chip (NoC) router

BagherzadehNader, LeeSeung Eun, 2009 .

Ultra-fast and efficient algorithm for energy optimization by gradient-based stochastic voltage and task scheduling

BagherzadehNader, H ChouPai, GorjiaraBita, 2007 .

Automatic compilation to a coarse-grained reconfigurable system-opn-chip

BagherzadehNader, NajjarWalid, VenkataramaniGirish, 2003 .

An ASIC design and formal analysis of a novel pipelined and parallel sorting accelerator

BagherzadehNader, TabriziNozar, 2008 .