Kia Bazargan

发表

Special Issue on the 2006 International Symposium on Field-Programmable Gate Arrays

Kia Bazargan, André DeHon, 2007 .

Timing-driven partitioning-based placement for island style FPGAs

Kia Bazargan, Pongstorn Maidee, Cristinel Ababei, 2005, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

A Novel Memory Structure for Embedded Systems: Flexible Sequential and Random Access Memory

Ying Chen, Kia Bazargan, Karthik Ranganathan, 2005, Journal of Computer Science and Technology.

Placement Method Targeting Predictability Robustness and Performance

Kia Bazargan, Cristinel Ababei, 2003, ICCAD 2003.

Hybrid binary-unary hardware accelerator

Kia Bazargan, S. Rasoul Faraji, 2019, ASP-DAC.

FPGA placement by graph isomorphism (abstract only)

Kia Bazargan, Hossein Omidian Savarbaghi, 2011, FPGA '11.

Thermal-aware floorplanning for task migration enabled active sub-threshold leakage reduction

Kia Bazargan, Hushrav Mogal, 2008, 2008 IEEE/ACM International Conference on Computer-Aided Design.

Low latency parallel implementation of traditionally-called stochastic circuits using deterministic shuffling networks

Kia Bazargan, Soheil Mohajer, Zhiheng Wang, 2018, 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC).

Timing minimization by statistical timing hMetis-based partitioning

Kia Bazargan, Cristinel Ababei, 2003, 16th International Conference on VLSI Design, 2003. Proceedings..

Incremental Placement for Timing Optimization

Kia Bazargan, Wonjoon Choi, K. Bazargan, 2003, ICCAD.

Randomness meets feedback: Stochastic implementation of logistic map dynamical system

Kia Bazargan, Arnd Scheel, Zhiheng Wang, 2015, 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC).

Thermal-aware floorplanning for task migration enabled active sub-threshold leakage reduction

Kia Bazargan, Hushrav Mogal, 2008, ICCAD 2008.

A Reconfigurable Architecture with Sequential Logic-Based Stochastic Computing

Kia Bazargan, Peng Li, David J. Lilja, 2017, ACM J. Emerg. Technol. Comput. Syst..

Hierarchical global floorplacement using simulated annealing and network flow area migration

Kia Bazargan, Wonjoon Choi, 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

IIR filters using stochastic arithmetic

Kia Bazargan, David J. Lilja, Marc D. Riedel, 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Sequential logic to transform probabilities

Kia Bazargan, Naman Saraf, 2013, 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Fast floorplanning for effective prediction and construction

Majid Sarrafzadeh, Kia Bazargan, Abhishek Ranjan, 2001, IEEE Trans. Very Large Scale Integr. Syst..

Routing Magic: Performing Computations Using Routing Networks and Voting Logic on Unary Encoded Data

Kia Bazargan, Soheil Mohajer, Zhiheng Wang, 2018, FPGA.

A Petri-Net Based Pre-Runtime Scheduler for Dynamically Self-Reconfiguration of FPGAs

Kia Bazargan, Jennifer G. Dy, Manoel Eusebio de Lima, 2005 .

Fast and Accurate Statistical Criticality Computation Under Process Variations

Kia Bazargan, Sachin S. Sapatnekar, Haifeng Qian, 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Logical Computation on Stochastic Bit Streams with Linear Finite-State Machines

Kia Bazargan, Peng Li, David J. Lilja, 2014, IEEE Transactions on Computers.

Session details: Poster session 1: architecture and CAD

Kia Bazargan, 2008, FPGA '08.

Using randomization to cope with circuit uncertainty

Kia Bazargan, Ehsan K. Ardestani, Hamid Safizadeh, 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

HBUCNNA: Hybrid Binary-Unary Convolutional Neural Network Accelerator

Kia Bazargan, Gaurav Singh, S. Rasoul Faraji, 2020, 2020 IEEE International Symposium on Circuits and Systems (ISCAS).

Guest Editorial

Kia Bazargan, André DeHon, A. DeHon, 2007, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

An efficient implementation of numerical integration using logical computation on stochastic bit streams

Chen Wang, Kia Bazargan, Peng Li, 2012, 2012 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

The synthesis of combinational logic to generate probabilities

Kia Bazargan, David J. Lilja, Weikang Qian, 2009, 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers.

Polynomial arithmetic using sequential stochastic logic

Kia Bazargan, Naman Saraf, 2016, 2016 International Great Lakes Symposium on VLSI (GLSVLSI).

Polysynchronous stochastic circuits

Kia Bazargan, David J. Lilja, Marc D. Riedel, 2016, 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC).

Session details: CAD 1

Kia Bazargan, K. Bazargan, 2006, FPGA '06.

Linear placement for static/dynamic reconfiguration in JBits

Kia Bazargan, Sharareh Noorbaloochi, Vamsi Krishna Marreddy, 2003, 11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2003. FCCM 2003..

Integrating scheduling and physical design into a coherent compilation cycle for reconfigurable computing architectures

Majid Sarrafzadeh, Kia Bazargan, Seda Ogrenci Memik, 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

Fast Template Placement for Reconfigurable Computing Systems

Majid Sarrafzadeh, Kia Bazargan, Ryan Kastner, 2000, IEEE Des. Test Comput..

HARP: hard-wired routing pattern FPGAs

Kia Bazargan, Gang Wang, Ryan Kastner, 2005, FPGA '05.

Stochastic functions using sequential logic

Kia Bazargan, David J. Lilja, Marc D. Riedel, 2013, 2013 IEEE 31st International Conference on Computer Design (ICCD).

Editorial: Special issue on dynamically adaptable embedded systems

Kia Bazargan, John Lach, 2004, TECS.

ACM/SIGDA International Symposium on Field Programmable Gate Arrays - FPGA

Gang Wang, Kia Bazargan, Ryan Kastner, 2005 .

Nostradamus: a floorplanner of uncertain designs

Majid Sarrafzadeh, Kia Bazargan, Samjung Kim, 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Physical Design for Three-Dimensional Circuits

Kia Bazargan, Sachin S. Sapatnekar, S. Sapatnekar, 2008, Handbook of Algorithms for Physical Design Automation.

Statistical timing driven partitioning for VLSI circuits

Kia Bazargan, Cristinel Ababei, K. Bazargan, 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

Multi-objective circuit partitioning for cutsize and path-based delay minimization

Kia Bazargan, George Karypis, Cristinel Ababei, 2002, IEEE/ACM International Conference on Computer Aided Design, 2002. ICCAD 2002..

Energy-Efficient Near-Sensor Convolution using Pulsed Unary Processing

Kia Bazargan, M. Hassan Najafi, S. Rasoul Faraji, 2019, 2019 IEEE 30th International Conference on Application-specific Systems, Architectures and Processors (ASAP).

Image analysis and partitioning for FPGA implementation of image restoration

Majid Sarrafzadeh, Kia Bazargan, S. Ogrenci, 2000, 2000 IEEE Workshop on SiGNAL PROCESSING SYSTEMS. SiPS 2000. Design and Implementation (Cat. No.00TH8528).

3-D Floorplanning: Simulated Annealing and Greedy Placement Methods for Reconfigurable Computing Systems

Majid Sarrafzadeh, Kia Bazargan, Ryan Kastner, 2000, Des. Autom. Embed. Syst..

Defect-Tolerant FPGA Architecture Exploration

Kia Bazargan, Pongstorn Maidee, K. Bazargan, 2006, 2006 International Conference on Field Programmable Logic and Applications.

Nostradamus: a floorplanner of uncertain design

Majid Sarrafzadeh, Kia Bazargan, Samjung Kim, 1998, ISPD '98.

Parallel Unary Computing Based on Function Derivatives

Kia Bazargan, Soheil Mohajer, Zhiheng Wang, 2020, ACM Trans. Reconfigurable Technol. Syst..

3-D floorplanning: simulated annealing and greedy placement methods for reconfigurable computing systems

Majid Sarrafzadeh, Kia Bazargan, Ryan Kastner, 1999, Proceedings Tenth IEEE International Workshop on Rapid System Prototyping. Shortening the Path from Specification to Prototype (Cat. No.PR00246).

Placement Method Targeting Predictability Robustness and Performance

Kia Bazargan, Cristinel Ababei, 2003, ICCAD.

Stochastic Implementation and Analysis of Dynamical Systems Similar to the Logistic Map

Kia Bazargan, Arnd Scheel, Zhiheng Wang, 2017, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Variation-aware routing for FPGAs

Kia Bazargan, Satish Sivaswamy, K. Bazargan, 2007, FPGA '07.

Three-dimensional place and route for FPGAs

Kia Bazargan, Cristinel Ababei, Hushrav Mogal, 2006, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Time-Encoded Values for Highly Efficient Stochastic Circuits

Kia Bazargan, Ramesh Harjani, David J. Lilja, 2017, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Low-Cost Approximate Constant Coefficient Hybrid Binary-Unary Multiplier for DSP Applications

Kia Bazargan, S. Rasoul Faraji, Pierre Abillama, 2020, 2020 IEEE 28th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM).

FPGA Synthesis and CAD for Reconfigurable Systems

Luca Benini, Stephen A. Edwards, Yunheung Paek, 2009 .

Microarchitecture floorplanning for sub-threshold leakage reduction

Kia Bazargan, Hushrav Mogal, 2007 .

Three-dimensional place and route for FPGAs

Kia Bazargan, Cristinel Ababei, Hushrav Mogal, 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

Improvements on Efficiency and Efficacy of SPFD-Based Rewiring for LUT-Based Circuits

Kia Bazargan, Pongstorn Maidee, 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A reconfigurable stochastic architecture for highly reliable computing

Xin Li, Kia Bazargan, David J. Lilja, 2009, GLSVLSI '09.

Enhancing the Memory Performance of Embedded Systems with the Flexible Sequential and Random Access Memory

Ying Chen, Kia Bazargan, Karthik Ranganathan, 2004, Asia-Pacific Computer Systems Architecture Conference.

Deterministic Shuffling Networks to Implement Stochastic Circuits in Parallel

Kia Bazargan, Soheil Mohajer, Zhiheng Wang, 2020, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A Generalized and Unified SPFD-Based Rewiring Technique

Kia Bazargan, Pongstorn Maidee, 2007, 2007 International Conference on Field Programmable Logic and Applications.

Session details: CAD for high-level synthesis and debug

Kia Bazargan, 2013, FPGA '13.

A reconfigurable FPGA-based readback signal generator for hard-drive read channel simulator

Jaekyun Moon, Kia Bazargan, Jinghuan Chen, 2002, DAC '02.

Incremental Placement for Timing Optimization

Kia Bazargan, Wonjoon Choi, 2003, ICCAD 2003.

Estimation and optimization of reliability of noisy digital circuits

Kia Bazargan, Marc D. Riedel, Satish Sivaswamy, 2009, 2009 10th International Symposium on Quality Electronic Design.

Non-contiguous linear placement for reconfigurable fabrics

Kia Bazargan, Cristinel Ababei, K. Bazargan, 2004, 18th International Parallel and Distributed Processing Symposium, 2004. Proceedings..

Proceedings - Design Automation Conference

Kia Bazargan, Arnd Scheel, Zhiheng Wang, 2015, DAC 2015.

Computation on Stochastic Bit Streams Digital Image Processing Case Studies

Kia Bazargan, David J. Lilja, Weikang Qian, 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Fast hierarchical floorplanning with congestion and timing control

Majid Sarrafzadeh, Kia Bazargan, Abhishek Ranjan, 2000, Proceedings 2000 International Conference on Computer Design.

Energy-Efficient Pulse-Based Convolution for Near-Sensor Processing

Kia Bazargan, David J. Lilja, M. Hassan Najafi, 2020, 2020 IEEE International Symposium on Circuits and Systems (ISCAS).

A floorplanner of uncertain designs

Kia Bazargan, 1997 .

Stochastic-binary convolutional neural networks with deterministic bit-streams

Kia Bazargan, David J. Lilja, Bingzhe Li, 2020 .

t-QuadPlace: Timing Driven Quadratic Placement using Quadrisection Partitioning for FPGAs (Abstact Only)

Kia Bazargan, Satya Prakash Upadhyay, Nimish Agashiwala, 2016, FPGA.

Synthesizing combinational logic to generate probabilities

Kia Bazargan, David J. Lilja, Weikang Qian, 2011 .

A tileable switch module architecture for homogeneous 3D FPGAs

Kia Bazargan, Morteza Saheb Zamani, M. S. Zamani, 2009, 2009 IEEE International Conference on 3D System Integration.

Statistical Analysis and Process Variation-Aware Routing and Skew Assignment for FPGAs

Kia Bazargan, Satish Sivaswamy, K. Bazargan, 2008, TRETS.

Axilog: Language support for approximate hardware design

Kia Bazargan, Hadi Esmaeilzadeh, Jongse Park, 2015, 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Session details: Technical Session 8: Applications

Kia Bazargan, 2015, FPGA 2015.

An Overview of Time-Based Computing with Stochastic Constructs

Kia Bazargan, Ramesh Harjani, David J. Lilja, 2017, IEEE Micro.

Advanced Techniques in Logic Synthesis, Optimizations and Applications

Kia Bazargan, David J. Lilja, Weikang Qian, 2011 .

Non-Contiguous Linear Placement for Reconfigurable Fabrics

Kia Bazargan, Cristinel Ababei, 2004, IPDPS.

Axilog: Abstractions for Approximate Hardware Design and Reuse

Kia Bazargan, Hadi Esmaeilzadeh, Jongse Park, 2015, IEEE Micro.

Accelerating Deterministic Bit-Stream Computing with Resolution Splitting

Kia Bazargan, David J. Lilja, Bingzhe Li, 2019, 20th International Symposium on Quality Electronic Design (ISQED).

Three-dimensional place and route for FPGAs

Kia Bazargan, Cristinel Ababei, Hushrav Mogal, 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

Session details: Variation and yield

Kia Bazargan, 2007, FPGA '07.

Session details: Synthesis for FPGAs

Evangeline F. Y. Young, Kia Bazargan, K. Bazargan, 2005, ASP-DAC '05.

FPGA 2018 chairs’ welcome

Kia Bazargan, Jason H. Anderson, 2018 .

HW/SW codesign incorporating edge delays using dynamic programming

Kia Bazargan, Karthikeyan Bhasyam, 2003, Euromicro Symposium on Digital System Design, 2003. Proceedings..

FSRAM: Flexible Sequential and Random Access Memory for Embedded Systems

Ying Chen, Kia Bazargan, Karthik Ranganathan, 2004 .

Low-Cost Sorting Network Circuits Using Unary Processing

Kia Bazargan, Marc D. Riedel, M. Hassan Najafi, 2018, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Fast and accurate estimation of floorplans in logic/high-level synthesis

Majid Sarrafzadeh, Kia Bazargan, Abhishek Ranjan, 2000, ACM Great Lakes Symposium on VLSI.

Binary stochastic implementation of digital logic

Kia Bazargan, Yanzi Zhu, Peiran Suo, 2014, FPGA.

HBUNN - Hybrid Binary-Unary Neural Network: Realizing a Complete CNN on an FPGA

Kia Bazargan, Gaurav Singh, Sayed Abdolrasouol Faraji, 2019, 2019 IEEE 37th International Conference on Computer Design (ICCD).

Session details: Poster Session III

Kia Bazargan, K. Bazargan, 2020 .

Multi-objective circuit partitioning for cutsize and path-based delay minimization

Kia Bazargan, George Karypis, Cristinel Ababei, 2002, ICCAD 2002.

Harnessing state-of-the-art internet of things labs to motivate first-year electrical and computer engineering students

Kia Bazargan, John Sartori, David John Orser, 2018 .

Fast scheduling and placement methods for C to hardware/software compilation

Majid Sarrafzadeh, Kia Bazargan, 2000, SPIE Optics East.

An Architecture for Fault-Tolerant Computation with Stochastic Logic

Xin Li, Kia Bazargan, David J. Lilja, 2011, IEEE Transactions on Computers.

FPGA family composition and effects of specialized blocks

Kia Bazargan, Pongstorn Maidee, Nagib Hakim, 2008, 2008 International Conference on Field Programmable Logic and Applications.

A fast SPFD-based rewiring technique

Kia Bazargan, Pongstorn Maidee, 2010, 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC).

Improving linear feedback shift registers using similarity transformations

Kia Bazargan, Naman Saraf, K. Bazargan, 2015, 2015 IEEE Dallas Circuits and Systems Conference (DCAS).

The synthesis of complex arithmetic computation on stochastic bit streams using sequential logic

Kia Bazargan, David J. Lilja, Weikang Qian, 2012, 2012 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Polysynchronous Clocking: Exploiting the Skew Tolerance of Stochastic Circuits

Kia Bazargan, David J. Lilja, Marc D. Riedel, 2017, IEEE Transactions on Computers.

Statistical Analysis and Design of HARP FPGAs

Kia Bazargan, Gang Wang, Ryan Kastner, 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

The synthesis of linear Finite State Machine-based Stochastic Computational Elements

Kia Bazargan, David J. Lilja, Weikang Qian, 2012, 17th Asia and South Pacific Design Automation Conference.

Placement and routing in 3D integrated circuits

Kia Bazargan, Yan Feng, Sachin S. Sapatnekar, 2005, IEEE Design & Test of Computers.

3D FPGAs: placement, routing, and architecture evaluation (abstract only)

Kia Bazargan, Cristinel Ababei, Hushrav Mogal, 2005, FPGA '05.

Microarchitecture Floorplanning for Sub-threshold Leakage Reduction

Kia Bazargan, Hushrav Mogal, 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

FPGA Technology Mapping, Placement, and Routing

Kia Bazargan, K. Bazargan, 2008, Handbook of Algorithms for Physical Design Automation.

Power and Area Efficient Sorting Networks Using Unary Processing

Kia Bazargan, David J. Lilja, Marc D. Riedel, 2017, 2017 IEEE International Conference on Computer Design (ICCD).

Clustering based pruning for statistical criticality computation under process variations

Kia Bazargan, Sachin S. Sapatnekar, Haifeng Qian, 2007, 2007 IEEE/ACM International Conference on Computer-Aided Design.

Energy-Efficient Convolutional Neural Networks with Deterministic Bit-Stream Processing

Kia Bazargan, David J. Lilja, Bingzhe Li, 2019, 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Fast timing-driven partitioning-based placement for island style FPGAs

Kia Bazargan, Pongstorn Maidee, Cristinel Ababei, 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

Clustering based pruning for statistical criticality computation under process variations

Kia Bazargan, Sachin S. Sapatnekar, Haifeng Qian, 2007, ICCAD 2007.

A memory optimized mersenne-twister random number generator

Kia Bazargan, Naman Saraf, 2017, 2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS).

Statistical Generic and Chip-Specific Skew Assignment for Improving Timing Yield of FPGAs

Kia Bazargan, Satish Sivaswamy, 2007, 2007 International Conference on Field Programmable Logic and Applications.

3D FPGAs: Placement, routing, and architecture evaluation

Kia Bazargan, Cristinel Ababei, Hushrav Mogal, 2005 .

A C to hardware/software compiler

Majid Sarrafzadeh, Kia Bazargan, Seda Ogrenci Memik, 2000, Proceedings 2000 IEEE Symposium on Field-Programmable Custom Computing Machines (Cat. No.PR00871).

Hybrid Binary-Unary Truncated Multiplication for DSP Applications on FPGAs

Kia Bazargan, S. Rasoul Faraji, K. Bazargan, 2020, 2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD).

Exploring Potential Benefits of 3D FPGA Integration

Kia Bazargan, Pongstorn Maidee, Cristinel Ababei, 2004, FPL.

Hybrid Binary-Unary Hardware Accelerator

Kia Bazargan, S. Rasoul Faraji, 2020, IEEE Transactions on Computers.

Case Studies of Logical Computation on Stochastic Bit Streams

Kia Bazargan, Peng Li, David J. Lilja, 2012, PATMOS.

Using Two-Dimensional Finite State Machine for Stochastic Computation

Kia Bazargan, David J. Lilja, Weikang Qian, 2012 .

Statistical Analysis and Design of HARP Routing Pattern FPGAs

Gang Wang, Kia Bazargan, Ryan Kastner, 2005 .