H. Hirano

2 V/100 ns 1 T/1 C nonvolatile ferroelectric memory architecture with bitline-driven read scheme and non-relaxation reference cell

N. Moriwaki, T. Sumi, H. Hirano, 1996, 1996 Symposium on VLSI Circuits. Digest of Technical Papers.

A 0.9-V 1T1C SBT-based embedded nonvolatile FeRAM with a reference voltage scheme and multilayer shielded bit-line structure

S. Iwanari, H. Hirano, T. Nakakuma, 2005, IEEE Journal of Solid-State Circuits.