Y.M. Lee

2Mb SPRAM Design: Bi-Directional Current Write and Parallelizing-Direction Current Read Schemes Based on Spin-Transfer Torque Switching

S. Ikeda, H. Ohno, H. Matsuoka, 2007, 2007 IEEE International Conference on Integrated Circuit Design and Technology.

Enhanced Stress Proximity Technique with Recessed S/D to Improve Device Performance at 45nm and Beyond

J. Sudijono, Y. Li, J. Li, 2008, 2008 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA).

A 45nm Low Cost Low Power Platform by Using Integrated Dual-Stress-Liner Technology

T. Hook, V. Sardesai, J. Sudijono, 2006, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..

32nm general purpose bulk CMOS technology for high performance applications at low voltage

S. Samavedam, M. Sherony, F. Arnaud, 2008, 2008 IEEE International Electron Devices Meeting.