Wolfgang Penth

A system of array families and synthesized soft arrays for the POWER9™ processor in 14nm SOI FinFET technology

Juergen Pille, G. Sapp, Michael Kugel, 2017, ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference.

A 32kB 2R/1W L1 data cache in 45nm SOI technology for the POWER7TM processor

Juergen Pille, Martin Eckert, Otto Wagner, 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).