Kavita Khare

发表

A Comparative Analysis Of Power Efficient Flip- Flops

Priyanka Sharma, Ganesh Lakshmana Kumar Moganti, Kavita Khare, 2012 .

An algorithmic approach for leakage current reduction in deep sub-micron CMOS circuits

Kavita Khare, Manikya Vara Prasad Done, Uday Panwar, 2014, 2014 International Conference on Advances in Electronics Computers and Communications.

Ultra-low power FinFET-based domino circuits

Kavita Khare, R. P. Singh, Tarun Kumar Gupta, 2017 .

Efficient Window-Architecture Design Using Completely Scaling-Free CORDIC Pipeline

Kavita Khare, Supriya Aggarwal, K. Khare, 2013, 2013 26th International Conference on VLSI Design and 2013 12th International Conference on Embedded Systems.

Hardware Efficient Architecture for Generating Sine/Cosine Waves

Kavita Khare, Supriya Aggarwal, 2012, 2012 25th International Conference on VLSI Design.

Hardware Efficient Algorithm for Complex Arithmetic

Kavita Khare, Nilay Khare, Supriya Aggarwal, 2009, 2009 IEEE International Advance Computing Conference.

Low-Power High Speed 1-bit Full Adder Circuit Design

Kavita Khare, Ajay Kumar Dadoria, Shailesh Dwivedi, 2016, ICTCS '16.

Leakage Power Reduction Technique by Using Multigate FinFET in DSM Technology

Kavita Khare, Ajay Kumar Dadori, T. K. Gupta, 2017 .

VCAT synchroniser - reduction of buffer size in VCAT enabled next generation SDH networks

Sunanda Manke, Kavita Khare, S. D. Sapre, 2011, Eur. Trans. Telecommun..

AC ANALYSIS OF CURRENT MIRROR AND FOLDED CASCODE OTA: A COMPARISON USING CADENCE TOOL

Ruchi Singh, Kavita Khare, Tarun Kumar Gupta, 2009 .

Noise Immunity Improvement in Dynamic CMOS circuits

Kavita Khare, Sunanda Ambulker, 2010 .

Concept, Design, and Implementation of Reconfigurable CORDIC

Kavita Khare, Pramod Kumar Meher, Supriya Aggarwal, 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A New Dual-Threshold Technique for Leakage Reduction in 65nm Footerless Domino Circuits

Kavita Khare, T. K. Gupta, 2013 .

Design of 45nm Switched Inverter Scheme (SIS) ADCs for Low Power and High Speed Applications

Arun Kumar Sunaniya, Kavita Khare, 2013 .

BackTrack Input Vector Algorithm for Leakage Reduction in CMOS VLSI Digital Circuit Design

Kavita Khare, Uday Panwar, 2014 .

Enhanced Buffer Router Design in NOC

Kavita Khare, Bhavana Prakash Shrivastava, 2012 .

Sleepy lector: A novel approach for leakage reduction in DSM technology

Kavita Khare, Ajay Kumar Dadoria, R. P. Singh, 2016, 2016 6th International Conference - Cloud System and Big Data Engineering (Confluence).

Design A 1Bit Low Power Full Adder Using Cadence Tool

Kavita Khare, Krishna Dayal Shukla, 2010 .

New Leakage Reduction Techniques for FinFET Technology with Its Application

Kavita Khare, Tarun Kumar Gupta, Ajay Kumar Dadoria, 2018, J. Circuits Syst. Comput..

A Combined Approach of IVC and GR for Leakage Power Reduction in CMOS VLSI Digital Circuit

Kavita Khare, Uday Panwar, 2014 .

A Wide Range 4.5 GHz VCO using 45nm CMOS Technology

Kavita Khare, Nidhi Thakur, 2012 .

Performance evaluation of domino logic circuits for wide fan-in gates with FinFET

Kavita Khare, Uday Panwar, Ajay Kumar Dadoria, 2018 .

Differential Delay Compensator -- A New Approach to Reduce Buffer Size in VCAT Enabled Next Generation SDH Networks

Sunanda Manke, Kavita Khare, S. D. Sapre, 2009, 2009 International Conference on Advances in Recent Technologies in Communication and Computing.

Smart Multicrossbar Router Design in NOC

Kavita Khare, Bhavana Prakash Shrivastava, 2013, VLSIC 2013.

Lector with Footed-Diode Inverter: A Technique for Leakage Reduction in Domino Circuits

Kavita Khare, Tarun Kumar Gupta, T. Gupta, 2013, Circuits Syst. Signal Process..

Design of Improved Resistor Less 45NM Switched Inverter Scheme (SIS) Analog to Digital Converter

Arun Kumar Sunaniya, Kavita Khare, 2013, VLSIC 2013.

Design Techniques Targeting Low-Area-Power-Delay Product in Hyperbolic CORDIC Algorithm

Kavita Khare, Supriya Aggarwal, 2012, Comput. J..

A Novel Approach for Leakage Power Reduction Techniques in 65nm Technologies

Kavita Khare, Ajay Kumar Dadoria, K. Khare, 2014 .

CORDIC-based window implementation to minimise area and pipeline depth

Kavita Khare, Supriya Aggarwal, K. Khare, 2013, IET Signal Process..

Design and Analysis of Low-Power Adiabatic Logic Circuits by Using CNTFET Technology

Kavita Khare, Ajay Kumar Dadoria, K. Khare, 2019, Circuits Syst. Signal Process..

Ultra Low Power High Speed Domino Logic Circuit by Using FinFET Technology

Kavita Khare, Tarun Kumar Gupta, Ajay Kumar Dadoria, 2016 .

Low Power-High Speed 11T Full Adder DSM Design

Kavita Khare, Ajay Kumar Dadoria, R. P. Singh, 2014 .

A Survey on Nano-Scale Double Gate CMOS Transistor

Kavita Khare, R. P. Singh, Ajay Kumar Dadoria, 2015 .

FPGA Design and Implementation Issues of Artificial Neural Network Based PID Controllers

Vikas Gupta, Kavita Khare, R. P. Singh, 2009, 2009 International Conference on Advances in Recent Technologies in Communication and Computing.

High Speed FPGA Implementation of FIR Filter for DSP Applications

Kavita Khare, Rakhi Thakur, Rakhi Thakur, 2013 .

FPGA Implementation of Cross Virtual Concatenation Transmitter/ Receiver for Data Transmission over Next Generation SDH Systems

Sunanda Manke, Kavita Khare, S. D. Sapre, 2012, J. Signal Process. Syst..

Comparison of pipelined IEEE-754 standard floating point multiplier with unpipelined multiplier

Kavita Khare, Nilay Khare, R. P. Singh, 2006 .

A Novel Approach for Reduction in CFO at Channel Estimator in WiMax OFDM System

Minal Saxena, Kavita Khare, 2012 .

Leakage Reduction by Integrating IVC and ALS Technique in 65 nm CMOS One Bit Adder Circuit

Kavita Khare, Uday Panwar, 2015 .

Scale-Free Hyperbolic CORDIC Processor and Its Application to Waveform Generation

Kavita Khare, Pramod Kumar Meher, Supriya Aggarwal, 2013, IEEE Transactions on Circuits and Systems I: Regular Papers.

Synchronization and Preamble Concept for Frame Detection in OFDM

Kavita Khare, Rakhi Thakur, 2013 .

Power and Area Efficient FLASH ADC Design using 65nm CMOS Technology

Kavita Khare, Ajay Kumar Dadoria, M. AbhilashKumar, 2014 .

Redesigned-Scale-Free CORDIC Algorithm Based FPGA Implementation of Window Functions to Minimize Area and Latency

Kavita Khare, Supriya Aggarwal, K. Khare, 2012, Int. J. Reconfigurable Comput..

3D CORDIC Algorithm Based Cartesian to Spherical Coordinate Converter

Kavita Khare, Anita Jain, 2013, VDAT.

A Novel Power Reduction Technique for Dual-Threshold Domino Logic in Sub-65nm Technology

Kavita Khare, T. K. Gupta, 2013, VLSIC 2013.

Standby leakage reduction in nanoscale CMOS VLSI circuits

Kavita Khare, J. Deshmukh, 2010, ICWET.

Gate replacement technique with thick Tox to mitigate leakage with zero delay penalty for DSM CMOS circuit

Kavita Khare, Uday Panwar, 2015, 2015 International Conference on Industrial Instrumentation and Control (ICIC).

Dynamic SVL and body bias for low leakage power and high performance in CMOS digital circuits

Kavita Khare, Jyoti Deshmukh, K. Khare, 2012 .

A New Technique for Leakage Reduction in 65 nm Footerless Domino Circuits

Kavita Khare, Tarun Kumar Gupta, 2013 .

Comparison of pipelined IEEE-754 standard floating point adder with unpipelined adder

Kavita Khare, Nilay Khare, R. P. Singh, 2005 .

Comparison of Leakage Current at Deep Sub Micron Technologies in CMOS Digital Circuit

Kavita Khare, Uday Panwar, 2014 .

A Novel High-Performance Lekage-Tolerant, Wide Fan-In Domino Logic Circuit in Deep-Submicron Technology

Kavita Khare, Ajay Kumar Dadoria, T. K. Gupta, 2015 .

Performance optimized digital QPSK modulator

Kavita Khare, Mansi Jain, Supriya Aggarwal, 2017, 2017 International Conference on Energy, Communication, Data Analytics and Soft Computing (ICECDS).

Integrating flipped drain and power gating techniques for efficient FinFET logic circuits

Kavita Khare, Uday Panwar, Ajay Kumar Dadoria, 2018 .

An Algorithm for Leakage Power Reduction through IVC in CMOS VLSI Digital Circuits

Kavita Khare, Manikya Vara Prasad Done, Uday Panwar, 2014 .

Patch Loaded DRA for Broadband WLAN Applications

Kavita Khare, S. C. Srivastava, Archana Sharma, 2013 .

100Mbps Ethernet data transmission over SDH networks using Cross Virtual Concatenation

Sunanda Manke, Kavita Khare, S. D. Sapre, 2008, 2008 16th IEEE International Conference on Networks.

A Novel Approach for Optimal Design of Sample Rate Conversion Filter Using Linear Optimization Technique

Kavita Khare, Bhavana P. Shrivastava, Divya Gautam, 2021, IEEE Access.

Area and Power Efficient Truncated Booth Multipliers Using Approximate Carry-Based Error Compensation

Kavita Khare, Zainab Aizaz, 2022, IEEE Transactions on Circuits and Systems II: Express Briefs.

Efficient Design and Fpga Implementation of Digital Controller Using Xilinx SysGen®

Kavita Khare, R. P. Singh, Vikas Gupta, 2010 .

Integrating sleep and pass transistor logic for leakage power reduction in FinFET circuits

Kavita Khare, Tarun Kumar Gupta, Ajay Kumar Dadoria, 2017 .

A Low power 50 nm Technology Based CMOS Inverter with Sleep Transistor Scheme

Arun Kumar Sunaniya, Kavita Khare, 2011 .

Leakage Reduction by Using FinFET Technique for Nanoscale Technology Circuits

Kavita Khare, Ajay Kumar Dadoria, T. Gupta, 2017 .

A Design Comparison of Low Power 50 nm Technology Based Inverter with Sleep Transistor and MTCMOS Scheme

Arun Kumar Sunaniya, Kavita Khare, Scholar MANIT, 2011 .