Kyung-Ju Cho

发表

Design of a Sample-Rate Converter From CD to DAT Using Fractional Delay Allpass Filter

Keshab K. Parhi, Kyung-Ju Cho, Ji-Suk Park, 2007, IEEE Transactions on Circuits and Systems II: Express Briefs.

Variable Length CAN Message Compression Using Bit Rearrangement

Kyung-Ju Cho, 2011 .

Sound Source Localization Method Using Region Selection

Kyung-Ju Cho, Jin-Gyun Chung, Chang-Ha Jeon, 2011 .

Memory Reduction Method of DIT-based IFFT Bit-Reversal

Kyung-Ju Cho, Jin-Gyun Chung, Zheyan Piao, 2015 .

Fixed-Width Modified Booth Multiplier Design Based on Error Bound Analysis

Dae-Ik Kim, Yong-Kab Kim, Kyung-Ju Cho, 2011, FGIT-MulGraB.

A memory size reduction method of pipelined IFFT processor for OFDM systems

Kyung-Ju Cho, In-Gul Jang, 2011, IEICE Electron. Express.

Low Power Small Area Modified Booth Multiplier Design for Predetermined Coefficients

Kyung-Ju Cho, Jin-Gyun Chung, Yong-Eun Kim, 2007, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Implementation of FlexRay communication controller protocol with application to a robot system

Kyung-Ju Cho, Jin-Gyun Chung, Yi-Nan Xu, 2008, 2008 15th IEEE International Conference on Electronics, Circuits and Systems.

Constant multiplier design using specialized bit pattern adders

Kyung-Ju Cho, Jin-Gyun Chung, Yi-Nan Xu, 2008, 2008 15th IEEE International Conference on Electronics, Circuits and Systems.

Design of Bit-Pattern Specialized Adder for Constant Multiplication

Kyung-Ju Cho, Yong-Eun Kim, 2008 .

Memory efficient DIT-based SDF IFFT for OFDM systems

Kyung-Ju Cho, Jin-Gyun Chung, Ho-Yun Lee, 2014, IEICE Electron. Express.

Adaptive Error Compensation for Low Error Fixed-Width Squarers

Kyung-Ju Cho, Jin-Gyun Chung, 2007, IEICE Trans. Inf. Syst..

Efficient IFFT architecture design for OFDM applications

Kyung-Ju Cho, Jin-Gyun Chung, Dae-Ho Kim, 2012, 2012 International SoC Design Conference (ISOCC).

Low latency IFFT design for 3GPP LTE

Kyung-Ju Cho, Jin-Gyun Chung, In-Gul Jang, 2016, 2016 International SoC Design Conference (ISOCC).

Memory efficient IFFT design for OFDM-based applications

Kyung-Ju Cho, Jin-Gyun Chung, Hwan-Yong Kim, 2013, IEICE Electron. Express.

Efficient unsigned squarer design techniques

Kyung-Ju Cho, 2012, IEICE Electron. Express.

Hardware Efficient QR Decomposition for GDFE

Kyung-Ju Cho, Jin-Gyun Chung, Yi-Nan Xu, 2007, 2007 IEEE Workshop on Signal Processing Systems.

Fixed-Width Group CSD Multiplier Design

Xinming Huang, Kyung-Ju Cho, Jin-Gyun Chung, 2010, IEICE Trans. Inf. Syst..

Low-latency and memory-efficient SDF IFFT processor design for 3GPP LTE

Kyung-Ju Cho, Jin-Gyun Chung, In-Gul Jang, 2017, IEICE Electron. Express.

CSD-Based Programmable Multiplier Design for Predetermined Coefficient Groups

Xinming Huang, Kyung-Ju Cho, Jin-Gyun Chung, 2010, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Memory Size Reduction Technique of SDF IFFT Architecture for OFDM-Based Applications

Kyung-Ju Cho, Jin-Gyun Chung, In-Gul Jang, 2012, IEICE Trans. Commun..

Design of low-error fixed-width modified booth multiplier

Keshab K. Parhi, Kyung-Ju Cho, Jin-Gyun Chung, 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Low error fixed-width modified Booth multiplier

Keshab K. Parhi, Kyung-Ju Cho, Jin-Gyun Chung, 2002, IEEE Workshop on Signal Processing Systems.

Error bound reduction for fixed-width modified Booth multiplier

Kyung-Ju Cho, Jin-Gyun Chung, Seong-Min Lee, 2004, Conference Record of the Thirty-Eighth Asilomar Conference on Signals, Systems and Computers, 2004..

Design of low error fixed-width squarer

Kyung-Ju Cho, Byeong-Kuk Kim, Jin-Gyun Chung, 2003, 2003 IEEE Workshop on Signal Processing Systems (IEEE Cat. No.03TH8682).

Power and Area Efficient Squarer Design

Yong-Eun Kim, Kyung-Ju Cho, Jin-Gyun Chung, 2006, 2006 Fortieth Asilomar Conference on Signals, Systems and Computers.