Khosrov Dabbagh-Sadeghipour

An efficient postprocessor architecture for channel mismatch correction of time interleaved ADCs

Asgar Abbaszadeh, Khosrov Dabbagh-Sadeghipour, 2010, 2010 18th Iranian Conference on Electrical Engineering.

A new FPGA-based postprocessor architecture for channel mismatch correction of time interleaved ADCS

Asgar Abbaszadeh, Khosrov Dabbagh-Sadeghipour, 2009, 2009 IEEE Workshop on Signal Processing Systems.

A new wideband, high-linear passive Sample and Hold structure suitable for high-speed, high-resolution ADCs

Khosrov Dabbagh-Sadeghipour, 2008, APCCAS.

Efficient realization of reconfigurable FIR filter using the new coefficient representation

Asgar Abbaszadeh, Khosrov Dabbagh-Sadeghipour, 2011, IEICE Electron. Express.

A new successive approximation architecture for high-speed low-power ADCs

Abdollah Khoei, Khayrollah Hadidi, Khosrov Dabbagh-Sadeghipour, 2006 .

ANEW FPGA-BASED POSTPROCESSORARCHITECTUREFOR CHANNEL MISMATCHCORRECTIONOF TIME INTERLEAVEDADCS

Khosrov Dabbagh-Sadeghipour, 2009 .

A new offset cancelled latch comparator for high-speed, low-power ADCs

Khosrov Dabbagh-Sadeghipour, 2010, 2010 IEEE Asia Pacific Conference on Circuits and Systems.

A new hardware efficient, low power FIR digital filter implementation approach

Ali Aghagolzadeh, Khosrov Dabbagh-Sadeghipour, 2003, 10th IEEE International Conference on Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003.

An accurate track-and-latch comparator

Khosrov Dabbagh-Sadeghipour, 2012, IEICE Electron. Express.

Design of a sample-and-hold analog front end for a 56Gb/s PAM-4 receiver using 65nm CMOS

Paul D. Townsend, Peter Ossieur, Khosrov Dabbagh-Sadeghipour, 2015, 2015 IEEE International Symposium on Circuits and Systems (ISCAS).