Daisuke Saida

Sub-3 ns pulse with sub-100 µA switching of 1x–2x nm perpendicular MTJ for high-performance embedded STT-MRAM towards sub-20 nm CMOS

Daisuke Saida, Saori Kashiwada, Megumi Yakabe, 2016, 2016 IEEE Symposium on VLSI Technology.

(Invited) Low Power Stt-Mram and Its Application to Normally-Off Processor

Daisuke Saida, Saori Kashiwada, Tadaomi Daibou, 2015 .

1×- to 2×-nm MTJ switching at sub-3 ns pulses with compatible current in sub-20 nm CMOS for high performance embedded STT-MRAM

Daisuke Saida, Saori Kashiwada, Megumi Yakabe, 2017, 2017 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA).

$1\times$ - to $2\times$ -nm perpendicular MTJ Switching at Sub-3-ns Pulses Below $100~\mu$ A for High-Performance Embedded STT-MRAM for Sub-20-nm CMOS

Daisuke Saida, Saori Kashiwada, Megumi Yakabe, 2017, IEEE Transactions on Electron Devices.

Precise Damage Observation in Ion-Beam Etched MTJ

Daisuke Saida, Tadaomi Daibou, Hiroaki Yoda, 2016, IEEE Transactions on Magnetics.

Low-Current High-Speed Spin-Transfer Switching in a Perpendicular Magnetic Tunnel Junction for Cache Memory in Mobile Processors

Daisuke Saida, Megumi Yakabe, Shinobu Fujita, 2014, IEEE Transactions on Magnetics.