Saori Kashiwada

Sub-3 ns pulse with sub-100 µA switching of 1x–2x nm perpendicular MTJ for high-performance embedded STT-MRAM towards sub-20 nm CMOS

Daisuke Saida, Saori Kashiwada, Megumi Yakabe, 2016, 2016 IEEE Symposium on VLSI Technology.

(Invited) Low Power Stt-Mram and Its Application to Normally-Off Processor

Daisuke Saida, Saori Kashiwada, Tadaomi Daibou, 2015 .

A 250-MHz 256b-I/O 1-Mb STT-MRAM with advanced perpendicular MTJ based dual cell for nonvolatile magnetic caches to reduce active power of processors

Saori Kashiwada, Hiroki Noguchi, Shinobu Fujita, 2013, 2013 Symposium on VLSI Circuits.

1×- to 2×-nm MTJ switching at sub-3 ns pulses with compatible current in sub-20 nm CMOS for high performance embedded STT-MRAM

Daisuke Saida, Saori Kashiwada, Megumi Yakabe, 2017, 2017 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA).

In situ monitoring of the growth of ice films by laser picosecond acoustics

Jeremy J. Baumberg, Roberto Li Voti, Osamu Matsuda, 2006 .

$1\times$ - to $2\times$ -nm perpendicular MTJ Switching at Sub-3-ns Pulses Below $100~\mu$ A for High-Performance Embedded STT-MRAM for Sub-20-nm CMOS

Daisuke Saida, Saori Kashiwada, Megumi Yakabe, 2017, IEEE Transactions on Electron Devices.