D. Chanemougame

SON (silicon-on-nothing) technological CMOS platform: highly performant devices and SRAM cells

M.-P. Samson, N. Planes, D. Delille, 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

Emerging silicon-on-nothing (SON) devices technology

Stephane Monfray, T. Skotnicki, D. Chanemougame, 2004 .

Localized SOI technology: an innovative Low Cost self-aligned process for Ultra Thin Si-film on thin BOX integration for Low Power applications

T. Ernst, S. Deleonibus, T. Skotnicki, 2007, 2007 IEEE International Electron Devices Meeting.

A 10nm platform technology for low power and high performance application featuring FINFET devices with multi workfunction gate stack on bulk and SOI

B. Lherron, D. Chanemougame, P. Oldiges, 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

FDSOI CMOS devices featuring dual strained channel and thin BOX extendable to the 10nm node

O. Faynot, Y. Escarabajal, B. Lherron, 2014, 2014 IEEE International Electron Devices Meeting.

Performance boost of scaled Si PMOS through novel SiGe stressor for HP CMOS

V. Fiori, S. Orain, D. Delille, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

Folded fully depleted Bulk+ technology as a highly W-scaled planar solution

G. Ghibaudo, G. Bidal, T. Skotnicki, 2008, ESSDERC 2008 - 38th European Solid-State Device Research Conference.

Planar Bulk+ technology using TiN/Hf-based gate stack for low power applications

G. Ghibaudo, G. Bidal, M. Rafik, 2008, 2008 Symposium on VLSI Technology.

10nm FINFET technology for low power and high performance applications

D. Chanemougame, P. Oldiges, B. Haran, 2014, 2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT).