A. Talbot

SON (silicon-on-nothing) technological CMOS platform: highly performant devices and SRAM cells

M.-P. Samson, N. Planes, D. Delille, 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

SON (Silicon-On-Nothing) P-MOSFETs with totally silicided (CoSi/sub 2/) polysilicon on 5 nm-thick Si-films: the simplest way to integration of metal gates on thin FD channels

M. Haond, T. Skotnicki, S. Monfray, 2002, Digest. International Electron Devices Meeting,.

High Density Planes Deposition Kinetics and Facets Propagation in Silicon Selective Epitaxial Growth

A. Talbot, D. Dutartre, N. Loubet, 2006, 2006 International SiGe Technology and Device Meeting.

Performance boost of scaled Si PMOS through novel SiGe stressor for HP CMOS

V. Fiori, S. Orain, D. Delille, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

Highly performant double gate MOSFET realized with SON process

D. Delille, T. Skotnicki, S. Monfray, 2003, IEEE International Electron Devices Meeting 2003.

Highly-performant 38 nm SON (silicon-on-nothing) P-MOSFETs with 9 nm-thick channels

M. Haond, T. Skotnicki, S. Monfray, 2002, 2002 IEEE International SOI Conference.

First 80 nm SON (Silicon-On-Nothing) MOSFETs with perfect morphology and high electrical performance

M. Haond, T. Skotnicki, S. Monfray, 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).