R. Palla

发表

SON (silicon-on-nothing) technological CMOS platform: highly performant devices and SRAM cells

M.-P. Samson, N. Planes, D. Delille, 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

Fully-depleted SOI process optimization for 60 nm CMOS transistors

T. Skotnicki, R. Palla, B. Giffard, 2003, 2003 IEEE International Conference on SOI.

Low cost 65nm CMOS platform for Low Power & General Purpose applications

M. Woo, N. Planes, R. Palla, 2004, Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004..

Comparison between matching parameters and fluctuations at the wafer level

R. Palla, R. Difrenza, P. Llinares, 2002, Proceedings of the 2002 International Conference on Microelectronic Test Structures, 2002. ICMTS 2002..

Tunnel Sonnenburg: TSM-Vortrieb unter schwierigen geologischen Bedingungen / Sonnenburg Tunnel: Roadheader drive under tricky geological conditions

R. Palla, R J Plinninger, 2013 .

Emerging silicon-on-nothing (SON) devices technology

Stephane Monfray, T. Skotnicki, D. Chanemougame, 2004 .

SON (Silicon-On-Nothing) P-MOSFETs with totally silicided (CoSi/sub 2/) polysilicon on 5 nm-thick Si-films: the simplest way to integration of metal gates on thin FD channels

M. Haond, T. Skotnicki, S. Monfray, 2002, Digest. International Electron Devices Meeting,.

A functional 0.69 /spl mu/m/sup 2/ embedded 6T-SRAM bit cell for 65 nm CMOS platform

J. Farkas, N. Planes, N. Revil, 2003, 2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407).

16 nm planar NMOSFET manufacturable within state-of-the-art CMOS process thanks to specific design and optimisation

T. Skotnicki, S. Monfray, D. Dutartre, 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

65 nm device manufacture using shaped E-Beam lithography

F. Leverd, R. Palla, M. Broekaart, 2003, Digest of Papers Microprocesses and Nanotechnology 2003. 2003 International Microprocesses and Nanotechnology Conference.

Highly performant double gate MOSFET realized with SON process

D. Delille, T. Skotnicki, S. Monfray, 2003, IEEE International Electron Devices Meeting 2003.

Advanced Junction Engineering for 60nm-CMOS Transistors

T. Skotnicki, R. Palla, M. Bidaud, 2002, 32nd European Solid-State Device Research Conference.

Highly-performant 38 nm SON (silicon-on-nothing) P-MOSFETs with 9 nm-thick channels

M. Haond, T. Skotnicki, S. Monfray, 2002, 2002 IEEE International SOI Conference.

Gate stack optimization for 65 nm CMOS low power and high performance platform

R. Palla, B. Tavel, C. Ortolland, 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..