Thierry Poiroux

Ultra-thin body and thin-BOX SOI CMOS technology analog figures of merit

O. Faynot, Denis Flandre, Jean-Pierre Raskin, 2012 .

Impact of Self-Heating on UTB MOSFET Parameters

O. Rozeau, Denis Flandre, Jean-Pierre Raskin, 2014 .

On the Optimization of Ebeam Lithography Using Hydrogen Silsesquioxane (HSQ) for Innovative Self-Aligned CMOS Process

Stephane Monfray, Frederic Boeuf, Thomas Skotnicki, 2013 .

Planar bonded double gate mos transistors down to LG = 10nm

Maud Vinet, S. Deleonibus, J. Widiez, 2005 .

Analog and RF modeling of FDSOI UTBB MOSFET using Leti-UTSOI model

Christophe Lallement, Jean-Michel Sallese, Michel Minondo, 2016, 2016 MIXDES - 23rd International Conference Mixed Design of Integrated Circuits and Systems.

Analysis of Gate Current Wafer Level Variability in Advanced FD-SOI MOSFETs

Andre Juge, Krishna Pradeep, T. A. Karatsori, 2018, 2018 48th European Solid-State Device Research Conference (ESSDERC).

Characterization Methodology and Physical Compact Modeling of in-Wafer Global and Local Variability

Gérard Ghibaudo, Krishna Pradeep, Patrick Scheer, 2018, 2018 IEEE International Electron Devices Meeting (IEDM).

Advanced SOI MOSFETs : structures and device physics

O. Faynot, S. Deleonibus, Anne Vandooren, 2005 .

Scaling issues for advanced SOI devices: Gate oxide tunneling, thin buried oxide, and ultrathin films

Frederic Allibert, Sorin Cristoloveanu, Jalal Jomaah, 2003 .