J. Faricelli

A novel method for extracting the two-dimensional doping profile of a sub-half micron MOSFET

Siegfried Selberherr, N. Khalil, J. Faricelli, 1994, Proceedings of 1994 VLSI Technology Symposium.

Ultra High Performance, Low Power 0.2 µm CMOS Microprocessor Technology and TCAD Requirements

Cheng-Liang Huang, J. Faricelli, A. Nasr, 1995 .

Examination of the time power law dependencies in hot carrier stressing of n-MOS transistors

J. Faricelli, B. Doyle, K. Mistry, 1997, IEEE Electron Device Letters.

Characterization of oxide trap and interface trap creation during hot-carrier stressing of n-MOS transistors using the floating-gate technique

D. Vuillaume, J. Faricelli, B.S. Doyle, 1993, IEEE Electron Device Letters.

IIB-8 Large signal switching response of submicron Si and GaAs MESFET's: Device vs circuit

J. Frey, J. Nulman, J. Faricelli, 1981, IEEE Transactions on Electron Devices.

IIA-9 1/2 µm Si MESFET logic devices

J. Nulman, J. Faricelli, P. Krusius, 1982, IEEE Transactions on Electron Devices.

The extraction of two-dimensional MOS transistor doping via inverse modeling

S. Selberherr, N. Khalil, J. Faricelli, 1995, IEEE Electron Device Letters.