Daniel G. Saab

发表

Case study of ATPG-based bounded model checking: verifying USB2.0 IP core

Qiang Qiang, Chia-Lun Chang, Daniel G. Saab, 2005, 2005 International Conference on Computer Design.

Critical Path Delay Reduction in FPGAs with Unbalanced Lookup Times

Daniel G. Saab, Fatih Kocan, Jason Meyer, 2007, ERSA.

Concurrent D-algorithm on reconfigurable hardware

Daniel G. Saab, Fatih Kocan, 1999, 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051).

Parallel switch-level simulation for VLSI

Daniel G. Saab, Jacob A. Abraham, Robert B. Mueller-Thuns, 1991, Proceedings of the European Conference on Design Automation..

Iterative simulation-based Genetics + Deterministic Techniques = Complete AtPG

Daniel G. Saab, Jacob A. Abraham, Youssef G. Saab, 1994, IEEE/ACM International Conference on Computer-Aided Design.

Fault modeling and testing of self-timed circuits

Daniel G. Saab, Andrew T. Yang, Stanford S. Guillory, 1991, Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's.

Complementary nano-electromechanical switches for ultra-low power embedded processors

Daniel G. Saab, Khawla Alzoubi, Massood Tabib-Azar, 2009, GLSVLSI '09.

An emulation model for sequential ATPG-based bounded model checking

Qiang Qiang, Daniel G. Saab, Jacob A. Abraham, 2005, International Conference on Field Programmable Logic and Applications, 2005..

Site Partitioning for Redundant Arrays of Distributed Disks

Daniel G. Saab, W. Kent Fuchs, Antoine N. Mourad, 1996, J. Parallel Distributed Comput..

Concurrent Hierarchical and Multilevel Simulation of VLSI Circuits

Daniel G. Saab, Jacob A. Abraham, Joseph T. Rahmeh, 1993, Simul..

Assigning Sites to Redundant Clusters in a Distributed Storage System

Daniel G. Saab, W. Kent Fuchs, Antoine N. Mourad, 1993, 1993 International Conference on Parallel Processing - ICPP'93.

Parallel-concurrent fault simulation

Daniel G. Saab, 1993, IEEE Trans. Very Large Scale Integr. Syst..

Initialization of Sequential Circuits and its Application to ATPG

Daniel G. Saab, Jalal A. Wehbeh, 1998, J. Electron. Test..

Dynamic fault diagnosis for sequential circuits on reconfigurable hardware

Daniel G. Saab, Fatih Kocan, 1998, Proceedings International Conference on Computer Design. VLSI in Computers and Processors (Cat. No.98CB36273).

Hierarchical multi-level fault simulation of large systems

David Blaauw, Daniel G. Saab, Jacob A. Abraham, 1990, J. Electron. Test..

Automatic Assertion Generation for Simulation, Formal Verification and Emulation

Daniel G. Saab, Jacob A. Abraham, Tong Zhang, 2017, 2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

Automatic Generation of Instructions to Robustly Test Delay Defects in Processors

Daniel G. Saab, Jacob A. Abraham, Ramtilak Vemu, 2007, 12th IEEE European Test Symposium (ETS'07).

Reducing verification overhead with RTL slicing

Qiang Qiang, Daniel G. Saab, Jacob A. Abraham, 2007, GLSVLSI '07.

New methods for parallel pattern fast fault simulation for synchronous sequential circuits

Daniel G. Saab, Ravishankar K. Iyer, Gwan S. Choi, 1993, Proceedings ETC 93 Third European Test Conference.

Exact Path Delay Fault Coverage Calculation of Partitioned Circuits

Daniel G. Saab, Lun Li, Fatih Kocan, 2009, IEEE Transactions on Computers.

Portable parallel logic and fault simulation

Daniel G. Saab, Jacob A. Abraham, Robert F. Damiano, 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

Functional abstraction of logic gates for switch-level simulation

David Blaauw, Daniel G. Saab, Jacob A. Abraham, 1991, Proceedings of the European Conference on Design Automation..

Hierarchical test generation for systems on a chip

Daniel G. Saab, Jacob A. Abraham, Raghuram S. Tupuri, 2000, VLSI Design 2000. Wireless and Digital Imaging in the Millennium. Proceedings of 13th International Conference on VLSI Design.

Design, Modeling, and Simulation of a New Nanoelectromechanical Switch for Low-Power Applications

Daniel G. Saab, Massood Tabib-Azar, Sijing Han, 2018, IEEE Transactions on Electron Devices.

Conditioned HDL Slicing A way to Speed-up Formal Verification

Daniel G. Saab, Jacob A. Abraham, Jen-Chieh Ou, 2006, 2006 49th IEEE International Midwest Symposium on Circuits and Systems.

Accessibility analysis on data flow graph: an approach to design for testability

Daniel G. Saab, Chienwen Wu, Chung-Hsing Chen, 1991, [1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors.

DFT & ATPG: together again

Daniel G. Saab, Ben Mathew, 1995, Proceedings of 1995 IEEE International Test Conference (ITC).

CHAMP: concurrent hierarchical and multilevel program for simulation of VLSI circuits

David Blaauw, Daniel G. Saab, Jacob A. Abraham, 1988, [1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers.

Iterative [simulation-based genetics + deterministic techniques]= complete ATPG0

Daniel G. Saab, Jacob A. Abraham, Youssef Saab, 1994, ICCAD.

Automatic Generation of Behavioral Models from Switch-Level Descriptions

David Blaauw, Daniel G. Saab, Jacob A. Abraham, 1989, 26th ACM/IEEE Design Automation Conference.

Delay modeling and timing of bipolar digital circuits

Daniel G. Saab, Andrew T. Yang, Ibrahim N. Hajj, 1988, 25th ACM/IEEE, Design Automation Conference.Proceedings 1988..

Switch-Level Logic Simulation of Digital Bipolar Circuits

Daniel G. Saab, Ibrahim N. Hajj, 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

HDL Program Slicing to Reduce Bounded Model Checking Search Overhead

Daniel G. Saab, Jacob A. Abraham, Jen-Chieh Ou, 2006, 2006 IEEE International Test Conference.

Hierarchical simulation of MOS circuits using extracted functional models

Daniel G. Saab, Jalal A. Wehbeh, 1992, Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors.

Derivation of signal flow for switch-level simulation

David Blaauw, Daniel G. Saab, Jacob A. Abraham, 1990, Proceedings of the European Design Automation Conference, 1990., EDAC..

Performance of Redundant Disk Array Organizations in Transaction Processing Environments

Daniel G. Saab, W. Kent Fuchs, Antoine N. Mourad, 1993, 1993 International Conference on Parallel Processing - ICPP'93.

MEMS based single device "XOR" and "aND" logic gates for LSI mechanical processors operating in high radiation environments

Daniel G. Saab, Massood Tabib-Azar, Massood Tabib-Azar, 2012 .

Formal verification using bounded model checking: SAT versus sequential ATPG engines

Daniel G. Saab, Jacob A. Abraham, Vivekananda M. Vedula, 2003, 16th International Conference on VLSI Design, 2003. Proceedings..

Ultra-low-Power Ultra-fast Hybrid CNEMS-CMOS FPGA

Daniel G. Saab, Fatih Kocan, Khawla Alzoubi, 2010, 2010 International Conference on Field Programmable Logic and Applications.

Circuit simulation for Nano-Electro-Mechanical switches VLSI circuits

Daniel G. Saab, Massood Tabib-Azar, Khawla Alzoubi, 2010, 2010 53rd IEEE International Midwest Symposium on Circuits and Systems.

Recovery Issues in Databases Using Redundant Disk Arrays

Daniel G. Saab, W. Kent Fuchs, Antoine N. Mourad, 1993, J. Parallel Distributed Comput..

Parallel and scalable architecture for solving SATisfiability on reconfigurable FPGA

Daniel G. Saab, Jacob A. Abraham, F. Kocan, 2000, Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044).

Single-device “XOR” and “AND” gates for high speed, very low power LSI mechanical processors

Daniel G. Saab, Massood Tabib-Azar, F. K. Chowdhury, 2012 .

Application of simple genetic algorithms to sequential circuit test generation

Elizabeth M. Rudnick, Janak H. Patel, Daniel G. Saab, 1994, Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC.

Verifying properties using sequential ATPG [IC design]

Daniel G. Saab, Jacob A. Abraham, Vivekananda M. Vedula, 2002, Proceedings. International Test Conference.

Correction to "ATPG for combinational circuits on configurable hardware"

Daniel G. Saab, F. Kocan, 2002, IEEE Trans. Very Large Scale Integr. Syst..

On the initialization of sequential circuits

Daniel G. Saab, Jalal A. Wehbeh, D. Saab, 1994, Proceedings., International Test Conference.

ESIFT: Efficient System for Error Injection

Daniel G. Saab, Jacob A. Abraham, Ninghan Tian, 2018, 2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS).

Augmented partial reset

Daniel G. Saab, Ben Mathew, 1993, ICCAD.

Ultralow-Power Reconfigurable Computing with Complementary Nano-Electromechanical Carbon Nanotube Switches

Daniel G. Saab, Swarup Bhunia, Massood Tabib-Azar, 2007, 2007 Asia and South Pacific Design Automation Conference.

Database recovery using redundant disk arrays

Daniel G. Saab, W. Kent Fuchs, Antoine N. Mourad, 1992, [1992] Eighth International Conference on Data Engineering.

Design of a scalable parallel switch-level simulator for VLSI

Daniel G. Saab, Jacob A. Abraham, Robert B. Mueller-Thuns, 1990, Proceedings SUPERCOMPUTING '90.

Ultra-low power NEMS FPGA

Daniel G. Saab, Massood Tabib-Azar, Sijing Han, 2012, 2012 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Single Trojan injection model generation and detection

Daniel G. Saab, Jacob A. Abraham, Harini Bhamidipati, 2016, 2016 17th Latin-American Test Symposium (LATS).

Automatic test vector cultivation for sequential VLSI circuits using genetic algorithms

Daniel G. Saab, Jacob A. Abraham, Youssef Saab, 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Compact NEMS FPGA design for harsh environment and low power requirement

Daniel G. Saab, Massood Tabib-Azar, Sijing Han, 2013, 2013 Transducers & Eurosensors XXVII: The 17th International Conference on Solid-State Sensors, Actuators and Microsystems (TRANSDUCERS & EUROSENSORS XXVII).

XOR" AND "AND" GATES FOR HIGH S R LSI MECHANICAL PROCESSORS

Daniel G. Saab, Faisal K. Chowdhury, N. Chappanda, 2011 .

CHEETA: Composition of hierarchical sequential tests using ATKET

Daniel G. Saab, Jacob A. Abraham, Praveen Vishakantaiah, 1993, Proceedings of IEEE International Test Conference - (ITC).

Initialization of Sequential Circuits and its Application to ATPG

Daniel G. Saab, Jalal A. Wehbeh, D. Saab, 1996, Proceedings of 14th VLSI Test Symposium.

Switch-level timing simulation of bipolar ECL circuits

Daniel G. Saab, Andrew T. Yang, Ibrahim N. Hajj, 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

CRIS: a test cultivation program for sequential VLSI circuits

Daniel G. Saab, Jacob A. Abraham, Youssef Saab, 1992, ICCAD.

Tutorial T4A: Formal Verification Techniques and Tools for Complex Designs

Daniel G. Saab, Jacob A. Abraham, 2007, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07).

VLSI logic and fault simulation on general-purpose parallel computers

Daniel G. Saab, Jacob A. Abraham, Robert F. Damiano, 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Dynamic Fault Diagnosis of Combinational and Sequential Circuits on Reconfigurable Hardware

Daniel G. Saab, Fatih Kocan, 2007, J. Electron. Test..

Back-end-of-the-line MEMS switches for power management, ESD and security

Daniel G. Saab, Massood Tabib-Azar, Nusrat Tazin, 2018 .

A massively-parallel easily-scalable satisfiability solver using reconfigurable hardware

Daniel G. Saab, José T. de Sousa, Miron Abramovici, 1999, DAC '99.

Complementary Nano-Electro-Mechanical Switch for ultra-low-power applications: Design and modeling

Daniel G. Saab, Khawla Alzoubi, Massood Tabib-Azar, 2011, 2011 12th International Symposium on Quality Electronic Design.

ATPG for combinational circuits on configurable hardware : Reconfigurable and Adaptive VLSI Systems

Daniel G. Saab, Fatih Kocan, 2001 .

Fault behavior dictionary for simulation of device-level transients

Daniel G. Saab, Ravishankar K. Iyer, Gwan S. Choi, 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).

CRIS: A test cultivation program for sequential VLSI circuits

Daniel G. Saab, Jacob A. Abraham, Youssef G. Saab, 1992, 1992 IEEE/ACM International Conference on Computer-Aided Design.

Hierarchical simulation of large system

Daniel G. Saab, 1991 .

Benchmarking Parallel Processing Platforms: An Applications Perspective

Daniel G. Saab, Jacob A. Abraham, Robert F. Damiano, 1993, IEEE Trans. Parallel Distributed Syst..

ATPG for combinational circuits on configurable hardware

Daniel G. Saab, Fatih Kocan, 2001, IEEE Trans. Very Large Scale Integr. Syst..

Satisfiability on reconfigurable hardware

Daniel G. Saab, Miron Abramovici, D. Saab, 1997, FPL.

A novel behavioral testability measure

Daniel G. Saab, Chung-Hsing Chen, 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

A Modular Reconfigurable Architecture for Efficient Fault Simulation in Digital Circuits

Daniel G. Saab, Jacob A. Abraham, Fatih Kocan, 2003, FPL.

Extraction based verification method for off the shelf integrated circuits

Daniel G. Saab, Fatih Kocan, Jacob Abraham, 2009, 2009 1st Asia Symposium on Quality Electronic Design.

Beta: behavioral testability analysis

Daniel G. Saab, Chienwen Wu, Chung-Hsing Chen, 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

A virtual diagnosis system

Daniel G. Saab, Faith Kocan, 2000 .

On selecting flip-flops for partial reset

Daniel G. Saab, Miron Abramovici, Ben Mathew, 1993, Proceedings of IEEE International Test Conference - (ITC).

Robust switch-level test generation

Daniel G. Saab, Ben Mathew, 1992, Digest of Papers. 1992 IEEE VLSI Test Symposium.

Checking nested properties using bounded model checking and sequential ATPG

Qiang Qiang, Daniel G. Saab, Jacob A. Abraham, 2006, 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06).

Behavioral synthesis for testability

Daniel G. Saab, Chung-Hsing Chen, 1992, ICCAD.

Dynamic fault diagnosis on reconfigurable hardware

Daniel G. Saab, Fatih Kocan, 1999, DAC '99.

Combining multiple DFT schemes with test generation

Daniel G. Saab, Ben Mathew, 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Formal Verification ATPG Search Engine Emulator (Abstract Only)

Daniel G. Saab, Jacob A. Abraham, Gregory Ford, 2015, FPGA.

Complimentary Nano-Electromechanical Carbon Nanotube Switches

Daniel G. Saab, Swarup Bhunia, Massood Tabib-Azar, 2006 .