B. Chung

Gate-Level Dual-Threshold Static Power Optimization Methodology (GDSPOM) Using Path-Based Static Timing Analysis (STA) Technique

J. B. Kuo, B. Chung, J. Kuo, 2006, PATMOS.

Gate-level dual-threshold static power optimization methodology (GDSPOM) for designing high-speed low-power SOC applications using 90nm MTCMOS technology

J. B. Kuo, B. Chung, 2006, 2006 IEEE International Symposium on Circuits and Systems.

Gate-level dual-threshold static power optimization methodology (GDSPOM) using path-based static timing analysis (STA) technique for SOC application

J. B. Kuo, B. Chung, 2008, Integr..

Development and testing of a cross-sectional area measurement tool for evaluating vein size

Ron Kikinis, Kelly H. Zou, B. Chung, 2005, Comput. Biol. Medicine.