Hiroto Yasuura

发表

Routing Methodology for Minimizing Crosstalk in SoC

Takashi Yamada, Atsushi Sakai, Yoshifumi Matsushita, 2003 .

Instruction scheduling to reduce switching activity of off-chip buses for low-power systems with caches

Hiroto Yasuura, Hiroyuki Tomiyama, Tohru Ishihara, 1998 .

Possibilities to miss predicting timing errors in canary flip-flops

Hiroto Yasuura, Toshinori Sato, Takanori Hayashida, 2011, 2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS).

Low-Power Architecture of a Digital Matched Filter for Direct-Sequence Spread-Spectrum Systems(Regular Section)

Takashi Yamada, Yoshifumi Matsushita, Hiroto Yasuura, 2003 .

A Design Method for Low Power Arithmetic Circuits Considering Input Patterns

Hiroto Yasuura, Masanori Muroyama, 安浦寛人, 2001 .

Slicing Algorithm for Delta - Delay VHDL Descriptions

Hiroto Yasuura, Mizuho Iwaihara, Shigeru Ichinose, 1995 .

Synthesis of Minimum-Cost Multilevel Logic Networks via Genetic Algorithm

Hiroto Yasuura, Hisao Koizumi, Barry Shackleford, 2000 .

Satsuki: An Integrated Processor Synthesis and Compiler Generation System (Special Issue on Synthesis and Verification of Hardware Design)

Hiroto Yasuura, Hiroyuki Tomiyama, Hisao Koizumi, 1996 .

A Language for Designing Module Generators (Special Issue on Synthesis and Verification of Hardware Design)

Hiroto Yasuura, Keikichi Tamaru, VasilyG. Moshnyaga, 1993 .

ON THE DEPTH OF COMBINATIONAL CIRCUITS REQUIRED TO COMPUTE SWITCHING FUNCTIONS.

Hiroto Yasuura, Shuzo Yajima, 1979 .

A New Algorithm and its Hardware Implementation for High Throughput Image Filtering

Hiroto Yasuura, Keikichi Tamaru, Farhad Fuad Islam, 1991 .

On Bus Architecture Design Considering Crosstalk

Hiroto Yasuura, Kei Hirose, 1999 .

A Study on Energy Reduction in Quality-driven Digital Wireless Communication Systems

徳永将之, Hiroto Yasuura, Masanori Muroyama, 2006 .

System LSI design methods for low power LSIs

Hiroto Yasuura, Tohru Ishihara, 2000 .

Simulation Model Generation for Architecture Evaluation using an Information Extraction Technique

Hiroto Yasuura, Hiroki Akaboshi, 2001 .

Energy Management Techniques for SOC Design

Hiroto Yasuura, Tohru Ishihara, Masanori Muroyama, 2006 .

An FPGA-Based Genetic Algorithm Machine

Hiroto Yasuura, Hisao Koizumi, Takashi Iwamoto, 2000 .

A Processor Architecture Protecting Secret Data from Hostile Software

Hiroto Yasuura, Tatsuya Mori, Koji Inoue, 2005 .

High-performance hardware design and implementation of genetic algorithms

Hiroto Yasuura, Hisao Koizumi, Barry Shackleford, 2001 .

PARALLEL EXHAUSTIVE SEARCH USING CONTENT ADDRESSABLE MEMORIES FOR SEVERAL NP-COMPLETE PROBLEMS

Hiroto Yasuura, Keikichi Tamaru, Taizo Tsujimoto, 1988 .

Program Slicing on VHDL Descriptions and Its Evaluation (Special Section on VLSI Design and CAD Algorithms)

Hiroto Yasuura, Mizuho Iwaihara, Shigeru Ichinose, 1998 .

Leakage Power Reduction Using Bitwidth Optimization

Hiroto Yasuura, Yun Cao, 安浦寛人, 2002 .

Experimental Analysis of Power Estimation Models of CMOS VLSI Circuits

Hiroto Yasuura, Tohru Ishihara, T. Ishihara, 1997 .

Mitigating Performance Loss in Aggressive DVS Using Dual-Sensing Flip-Flops

Hiroto Yasuura, 佐藤寿倫, Toshinori Sato, 2008 .

Low-Energy Memory Allocation and Assignment Based on Variable Analysis for Application-Specific Systems

Hiroto Yasuura, Yun Cao, Takanori Okuma, 2002 .

An Accelerated Datapath Width Optimization Technique for Area Reduction of Embedded Systems

Hiroto Yasuura, 安浦寛人, Yun Cao, 2002 .

Parallel exhaustive search for several NP-complete problems using content addressable memories

Hiroto Yasuura, Keikichi Tamaru, T. Tsujimoto, 1988, 1988., IEEE International Symposium on Circuits and Systems.

Power Optimization by Datapath Width Adjustment

Hiroto Yasuura, Hiroyuki Tomiyama, 2002 .

Soft-Core Processor Architecture for Embedded System Design

Hiroto Yasuura, Hiroyuki Tomiyama, Akihiko Inoue, 1998 .

Variety of System LSIs and Their Advanced Applications

Hiroto Yasuura, 2007 .

Generating Secure Session Keys from Shared Secret Information for Multi-Application IC-card Systems

Hiroto Yasuura, Tatsuya Mori, Koji Inoue, 2005 .

Design Method for Real - Time Systems using Task Periodicity

Hiroto Yasuura, Hideaki Fujikake, 1998 .

A Design Method for a Low Power Digital FIR Filter in Digital Wireless communication systems

Hiroto Yasuura, Masanori Muroyama, 安浦寛人, 2004 .

Basic experimentation on accuracy of power estimation for CMOS VLSI circuits

Hiroto Yasuura, Tohru Ishihara, 1996, Proceedings of 1996 International Symposium on Low Power Electronics and Design.

Programmable power management architecture for power reduction

Hiroto Yasuura, Tohru Ishihara, 1998 .

A proposal of a reliability metric for dependable LSIs

Hiroto Yasuura, Toshinori Sato, 寛人安浦, 2012 .

An On-Chip Bus Architecture for Post-Fabrication Performance Compensation

Hiroto Yasuura, Masanori Muroyama, 安浦寛人, 2007 .

Embedded system cost optimization via data path width adjustment

Hiroto Yasuura, Hiroyuki Tomiyama, Hisao Koizumi, 1997 .

A digital filter design method of a baseband processor in a digital wireless communication system for low power

Hiroto Yasuura, 安浦寛人, 辻本泰造, 2003 .

An ILP Model of Code Placement Problem for Minimizing the Energy Consumption in Embedded Processors

Hiroto Yasuura, Tohru Ishihara, Masanori Muroyama, 2007 .

A Framework for Bitwidth Optimization in System-on-Chip Design

Hiroto Yasuura, Hiroyuki Tomiyama, 冨山宏之, 2002 .

TIME FIRST EVALUATION ALGORITHM FOR HIGH-SPEED LOGIC SIMULATION.

Hiroto Yasuura, Nagisa Ishiura, Shuzo Yajima, 1984 .

A Study of Dependence on Gate Depth/Width for Analyzing Delay/Power Variations in 90nm CMOS Circuits

Hiroto Yasuura, Yuan Yang, Masanori Muroyama, 2007 .

The ParallelEnumeration Sorting Scheme for

Hiroto Yasuura, Shuzo Yajima, Naofumi Takagi, 1982 .

A new VLSI algorithm for high throughput image filtering

Hiroto Yasuura, Keikichi Tamaru, Farhad Fuad Islam, 1992, [Proceedings] 1992 IEEE International Symposium on Circuits and Systems.

Measurement of Delay and Power Variation in 90nm CMOS Circuits

Hiroto Yasuura, Masanori Muroyama, Yuan Yang, 2006 .

A Bit-Parallel Block-Parallel Functional Memory Type Parallel Processor Architecture (Special Issue on New Architecture LSIs)

Hiroto Yasuura, Hidetoshi Onodera, Keikichi Tamaru, 1993 .

A-3-18 A Low Power Technique for Processor Based Embedded Systems by Using Clock Gating Instructions

Hiroto Yasuura, Masanori Muroyama, 安浦寛人, 2007 .

A Low-Energy Memory Design Technique Based on Variable Analysis for Application-Specific Systems

Hiroto Yasuura, Yun Cao, 安浦寛人, 2002 .

Redundant Coding and Local Computability in Parallel Computation(Mathematical Foundations of Computer Science and Their Applications)

Hiroto Yasuura, Shuzo Yajima, Naofumi Takagi, 1985 .

Pre-route power analysis techniques for SoC

Yoshifumi Matsushita, Hiroto Yasuura, Takashi Yamada, 2003 .

Towards Modeling Stored-value Electronic Money Systems

Hiroto Yasuura, Shunsuke Inenaga, Kenichiro Oyama, 2010 .

A Memory Power Optimization Technique for Application Specific Embedded Systems (Special Section on VLSI Design and CAD Algorithms)

Hiroto Yasuura, Tohru Ishihara, T. Ishihara, 1999 .

DESIGN OF ASYNCHRONOUS ARBITERS FROM THE STANDPOINT OF ASYNCHRONOUS SEQUENTIAL CIRCUIT THEORY.

Hiroto Yasuura, Shuzo Yajima, H. Yasuura, 1978 .

CMOS system LSI for processing IEEE 802.11B WLAN PHY signals through digital, analog baseband, and RF

Hiroto Yasuura, K. Yoshida, Haruichi Kanaya, 2004, The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings..

Unlinkable Identification for Large-scale RFID Systems

Hiroto Yasuura, Sozo Inoue, Yasunobu Nohara, 2006 .

Special Session: ecuriuy on SOG

Hiroto Yasuura, Naofumi Takagi, Srivaths Ravi, 2002 .

A HW/SW co-design environment for multi-media equipments development using inverse problem

Hiroto Yasuura, Hisao Koizumi, K. Yamamoto, 1997, Proceedings of 5th International Workshop on Hardware/Software Co Design. Codes/CASHE '97.

Video Quality Modeling for Quality-driven Design

Hiroto Yasuura, Yun Cao, 安浦寛人, 2001 .

Towards the system LSI design technology

Hiroto Yasuura, 2001 .

A Novel Test Technique in the SOC Era

Hiroto Yasuura, Makoto Sugihara, 安浦寛人, 2001 .

A case study of Short Term Cell-Flipping technique for mitigating NBTI degradation on cache

Hiroto Yasuura, Toshinori Sato, Yuji Kunitake, 2010, 2nd Asia Symposium on Quality Electronic Design (ASQED).

Single-Cycle-Accessible Two-Level Cache Architecture

Hiroto Yasuura, 安浦寛人, 石原亨, 2009 .

Automatic generation of command level simulation model of a processor from rt level description

Hiroto Yasuura, Hiroki Akaboshi, 1996 .

A bus delay reduction technique considering crosstalk

Hiroto Yasuura, Kei Hirose, 2002 .

Functional information extraction from combinational circuits

Hiroto Yasuura, Keikichi Tamaru, Masahiko Ohmura, 1991 .

A Hybrid Memory Architecture for Low Power Embedded System Design

Hiroto Yasuura, 安浦寛人, 石飛百合子, 2007 .

A Power Reduction Technique for an Equalization Circuit Using Adaptive Bitwidth Control

Hiroto Yasuura, Masanori Muroyama, Kousuke Tarumi, 2004 .

ON THE AREA OF LOGIC CIRCUITS IN VLSI.

Hiroto Yasuura, Shuzo Yajima, 1982 .

Behavioral verification of cpus using functional information extraction

Hiroto Yasuura, Keikichi Tamaru, Masahiko Ohmura, 1994 .

A Power Reduction Method for Low-Precision Computation

Hiroto Yasuura, Masanori Muroyama, 安浦寛人, 2005 .

A Simulation Study on Missing of Timing Errors on Canary Technique

Hiroto Yasuura, 佐藤寿倫, Toshinori Sato, 2008 .

Evaluation of Compiler Generator for Computer Architecture Evaluation

Hiroto Yasuura, Hiroyuki Tomiyama, 冨山宏之, 1994 .

Variable Pipeline Depth Processor for Energy Efficient Systems

Hiroto Yasuura, Masanori Muroyama, Akihiko Hyodo, 2003 .

FOREWORD (Special Issue on Synthesis and Verification of Hardware Design)

Daniel D. Gajski, Hiroto Yasuura, Hidetoshi Onodera, 1996 .

A digital filter optimization method for low power digital wireless communication system

Hiroto Yasuura, Kousuke Tarumi, Taizo Tsujimoto, 2003 .

Exploiting Narrow Bitwidth Operations for Low Power Embedded Software Optimization

Hiroto Yasuura, 安浦寛人, 石原亨, 2006 .

A Non-Uniform Cache Architecture for Reducing the Energy Consumption of Embedded Systems

Hiroto Yasuura, Masanori Muroyama, 安浦寛人, 2008 .

Low-Energy Design Using Datapath Width Optimization for Embedded Processor-Based Systems

Hiroto Yasuura, Yun Cao, 安浦寛人, 2002 .

Smart sensors and systems: Technology advancement and application demonstrations

Hiroto Yasuura, Youn-Long Lin, Chong-Min Kyung, 2020 .

An identifiable yet unlinkable authentication system with smart cards for multiple services

Hiroto Yasuura, Shunsuke Inenaga, Daisuke Ikeda, 2010 .

An Evaluation of Parallel Multipliers using Neuron MOS Transistors

Hiroto Yasuura, Kei Hirose, 1996 .