Jeong-Don Lim

13.1 A 1Tb 4b/cell NAND Flash Memory with tPROG=2ms, tR=110µs and 1.2Gb/s High-Speed IO Rate

Jiyoon Park, Dae-Seok Byeon, Jisu Kim, 2020, 2020 IEEE International Solid- State Circuits Conference - (ISSCC).

7.6 1GB/s 2Tb NAND flash multi-chip package with frequency-boosting interface chip

Sunghoon Kim, Jin-Tae Kim, Min-Jae Lee, 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.

A 7Gb/s/pin GDDR5 SDRAM with 2.5ns bank-to-bank active time and no bank-group restriction

Jae-Hyung Lee, Young-Hyun Jun, Dong-Min Kim, 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

A 40nm 2Gb 7Gb/s/pin GDDR5 SDRAM with a programmable DQ ordering crosstalk equalizer and adjustable clock-tracking BW

Young-Hyun Jun, Dae-Hyun Kim, Young-Sik Kim, 2011, 2011 IEEE International Solid-State Circuits Conference.

A 1Tb 4b/cell 64-stacked-WL 3D NAND flash memory with 12MB/s program throughput

Kyungmin Kim, Ki-Whan Song, Jonghoon Park, 2018, 2018 IEEE International Solid - State Circuits Conference - (ISSCC).

A 7 Gb/s/pin 1 Gbit GDDR5 SDRAM With 2.5 ns Bank to Bank Active Time and No Bank Group Restriction

Jae-Hyung Lee, Young-Hyun Jun, Dong-Min Kim, 2011, IEEE Journal of Solid-State Circuits.