S. Suhard

Integrated clean for TSV: Comparison between dry process and wet processes and their electrical qualification

S. Van Huylenbroeck, S. Suhard, Y. Li, 2016, 2016 IEEE 18th Electronics Packaging Technology Conference (EPTC).

Junctionless gate-all-around lateral and vertical nanowire FETs with simplified processing for advanced logic and analog/RF applications and scaled SRAM cells

B. Parvais, B. Kaczer, E. Simoen, 2016, 2016 IEEE Symposium on VLSI Technology.

Integration of the ZoneBOND™ temporary bonding material in backside processing for 3D applications

E. Beyne, A. Jourdain, A. La Manna, 2012, 2012 4th Electronic System-Integration Technology Conference.

Development of an all-in one wet single wafer process for 3D-SIC bump integration and its monitoring

M. Liebens, J. Slabbekoorn, S. Suhard, 2016, 2016 IEEE 18th Electronics Packaging Technology Conference (EPTC).

Temporary wafer bonding defect impact assessment on substrate thinning: Process enhancement through systematic defect track down

E. Beyne, A. Jourdain, S. Suhard, 2012, 2012 IEEE 62nd Electronic Components and Technology Conference.

Gate-last vs. gate-first technology for aggressively scaled EOT logic/RF CMOS

H. Bender, G. Eneman, N. Horiguchi, 2011, 2011 Symposium on VLSI Technology - Digest of Technical Papers.