Maria J. Avedillo

发表

Self-latching operation of MOBILE circuits using series-connection of RTDs and transistors

Maria J. Avedillo, José M. Quintana, Héctor Pettenghi, 2006, IEEE Transactions on Circuits and Systems II: Express Briefs.

Novel pipeline architectures based on Negative Differential Resistance devices

Juan Núñez, Maria J. Avedillo, José M. Quintana, 2013, Microelectron. J..

Analysis of frequency divider RTD circuits

Maria J. Avedillo, José M. Quintana, M. Avedillo, 2005, IEEE Transactions on Circuits and Systems I: Regular Papers.

Monostable-Bistable Transition Logic Elements: Threshold Logic vs. Boolean Logic Comparison

David Bol, Jean-Didier Legat, Maria J. Avedillo, 2006, 2006 13th IEEE International Conference on Electronics, Circuits and Systems.

Comparative Analysis of Projected Tunnel and CMOS Transistors for Different Logic Application Areas

Maria J. Avedillo, Juan Nunez, M. Avedillo, 2016, IEEE Transactions on Electron Devices.

VLSI implementations of threshold logic-a comprehensive survey

Valeriu Beiu, Maria J. Avedillo, José M. Quintana, 2003, IEEE Trans. Neural Networks.

Operation Limits for RTD-Based MOBILE Circuits

Juan Núñez, Maria J. Avedillo, José M. Quintana, 2009, IEEE Transactions on Circuits and Systems I: Regular Papers.

Novel Dynamic Gate Topology for Superpipelines in DSM Technologies

Juan Núñez, Maria J. Avedillo, José M. Quintana, 2013, 2013 Euromicro Conference on Digital System Design.

Using multi-threshold threshold gates in RTD-based logic design: A case study

Maria J. Avedillo, José M. Quintana, Héctor Pettenghi, 2005, Microelectron. J..

SMAS: a program for the concurrent state reduction and state assignment of finite state machines

Maria J. Avedillo, José M. Quintana, José L. Huertas, 1991, 1991., IEEE International Sympoisum on Circuits and Systems.

Improving robustness of dynamic logic based pipelines

Maria J. Avedillo, Juan Nunez, Hector J. Quintero, 2015, 2015 Conference on Design of Circuits and Integrated Systems (DCIS).

Single phase MOS-NDR mobile networks

Juan Núñez, Maria J. Avedillo, José M. Quintana, 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.

A new method for the state reduction of incompletely specified finite sequential machines

José Luis Huertas, Maria J. Avedillo, José M. Quintana, 1990, Proceedings of the European Design Automation Conference, 1990., EDAC..

A novel contribution to the RTD-based threshold logic family

Maria J. Avedillo, José M. Quintana, Héctor Pettenghi, 2008, 2008 IEEE International Symposium on Circuits and Systems.

Easily testable PLA-based FSMS

José Luis Huertas, Maria J. Avedillo, José M. Quintana, 1993, 1993 IEEE International Symposium on Circuits and Systems.

Review of Differential Threshold Gate Implementations

Valeriu Beiu, Maria J. Avedillo, José M. Quintana, 2003, Neural Networks and Computational Intelligence.

Simplified single-phase clock scheme for MOBILE networks

Maria J. Avedillo, José M. Quintana, Juan Nunez, 2011 .

Simple parallel weighted order statistic filter implementations

Esther Rodríguez-Villegas, Maria J. Avedillo, José M. Quintana, 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

Evaluation of RTD-CMOS Logic Gates

Juan Núñez, Maria J. Avedillo, José M. Quintana, 2010, 2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools.

DOE based high-performance gate-level pipelines

Juan Núñez, Maria J. Avedillo, Hector J. Quintero, 2014, 2014 24th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS).

A dynamic model for the state assignment problem

José Luis Huertas, Maria J. Avedillo, José M. Quintana, 1998, Proceedings Design, Automation and Test in Europe.

A quasi-differential quantizer based on SMOBILE

Juan Núñez, Maria J. Avedillo, José M. Quintana, 2007, SBCCI '07.

Efficient realization of RTD-CMOS logic gates

Juan Núñez, Maria J. Avedillo, José M. Quintana, 2011, GLSVLSI '11.

An improved RNS generator 2n ± k based on threshold logic

Ricardo Chaves, Leonel Sousa, Maria J. Avedillo, 2010, 2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip.

Impact of the RT-level architecture on the power performance of tunnel transistor circuits

Juan Núñez, Maria J. Avedillo, 2018, Int. J. Circuit Theory Appl..

COPAS: A New Algorithm for the Partial Input Encoding Problem

José Luis Huertas, Maria J. Avedillo, José M. Quintana, 2002, VLSI Design.

Exploring logic architectures suitable for TFETs devices

Juan Núñez, Maria J. Avedillo, M. Avedillo, 2017, 2017 IEEE International Symposium on Circuits and Systems (ISCAS).

Assessing application areas for tunnel transistor technologies

Maria J. Avedillo, Juan Nunez, M. Avedillo, 2015, 2015 Conference on Design of Circuits and Integrated Systems (DCIS).

νMOS-based Sorter for Arithmetic Applications

Gloria Huertas, Esther Rodríguez-Villegas, Adoración Rueda, 2000, VLSI Design.

Experimental Validation of a Two-Phase Clock Scheme for Fine-Grained Pipelined Circuits Based on Monostable to Bistable Logic Elements

Juan Núñez, Maria J. Avedillo, José M. Quintana, 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Bifurcation diagrams in MOS-NDR frequency divider circuits

Juan Núñez, Maria J. Avedillo, José M. Quintana, 2012, 2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012).

Non Return Mobile Logic Family

Maria J. Avedillo, José M. Quintana, Héctor Pettenghi, 2007, 2007 IEEE International Symposium on Circuits and Systems.

Limits to a Correct Evaluation in RTD-Based Quaternary Inverters

Juan Núñez, Maria J. Avedillo, José M. Quintana, 2007, 37th International Symposium on Multiple-Valued Logic (ISMVL'07).

Area-optimised registers using a folded PLA

Maria J. Avedillo, José M. Quintana, José L. Huertas, 1990 .

Efficient Realization of a Threshold Voter for Self-Purging Redundancy

José Luis Huertas, Maria J. Avedillo, José M. Quintana, 2001, J. Electron. Test..

Compact and Power Efficient MOS-NDR Muller C-Elements

Juan Núñez, Maria J. Avedillo, José M. Quintana, 2012, DoCEIS.

Limits to a correct operation in RTD-based ternary inverters

Juan Núñez, Maria J. Avedillo, José M. Quintana, 2008, 2008 IEEE International Symposium on Circuits and Systems.

LP-LV high-performance monolithic DTMF receiver with on-chip test facilities

Gloria Huertas, Maria J. Avedillo, Adoracion Rueda, 2003, SPIE Microtechnologies.

PRACTICAL LOW-COST CMOS REALIZATION OF COMPLEX LOGIC FUNCTIONS

Maria J. Avedillo, José M. Quintana, Adoración Rueda, 1995 .

Impact of pipeline in the power performance of tunnel transistor circuits

Juan Núñez, Maria J. Avedillo, 2016, 2016 26th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS).

Programmable logic gate based on resonant tunnelling devices

Maria J. Avedillo, José M. Quintana, Héctor Pettenghi, 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

Simplified Reed-Muller expressions for residue threshold functions

José Luis Huertas, Maria J. Avedillo, José M. Quintana, 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

Two-criterial constraint-driven FSM state encoding for low power

Steffen Rülke, Maria J. Avedillo, Manfred Koegst, 2001, Proceedings Euromicro Symposium on Digital Systems Design.

Design Guides for a Correct DC Operation in RTD-based Threshold Gates

Juan Núñez, Maria J. Avedillo, José M. Quintana, 2006, 9th EUROMICRO Conference on Digital System Design (DSD'06).

Operation limits in RTD-based ternary quantizers

Juan Núñez, Maria J. Avedillo, José M. Quintana, 2007, GLSVLSI '07.

Limits to a Correct Evaluation in RTD-based Ternary Inverters

Juan Núñez, Maria J. Avedillo, José M. Quintana, 2006, 2006 13th IEEE International Conference on Electronics, Circuits and Systems.

An encoding technique for low power CMOS implementations of controllers

Maria J. Avedillo, José M. Quintana, Manuel Martínez, 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

Analysis of the critical rise time in MOBILE-based circuits

Maria J. Avedillo, José M. Quintana, M. Avedillo, 2008, 2008 15th IEEE International Conference on Electronics, Circuits and Systems.

Review of Capacitive Threshold Gate Implementations

Valeriu Beiu, Maria J. Avedillo, José M. Quintana, 2003, ICANN.

An algorithm for face-constrained encoding of symbols using minimum code length

José Luis Huertas, Maria J. Avedillo, José M. Quintana, 1999, Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078).

Self-latching operation limits for MOBILE circuits

Maria J. Avedillo, José M. Quintana, Héctor Pettenghi, 2006, 2006 IEEE International Symposium on Circuits and Systems.

Logic models supporting the design of MOBILE-based RTD circuits

Maria J. Avedillo, José M. Quintana, Héctor Pettenghi, 2005, 2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05).

Improving delay-noise trade-off of dynamic gates for fine-grained pipelined applications

Maria J. Avedillo, José M. Quintana, Juan Nunez, 2013 .

A practical floating-gate Muller-C element using vMOS threshold gates

Gloria Huertas, Esther Rodriguez-Villegas, Adoración Rueda, 2001 .

Synthesis for testability of PLA based finite state machines

Maria J. Avedillo, José L. Huertas, J. M. Quintana, 1992, Proceedings First Asian Test Symposium (ATS `92).

Fast and area efficient multi-input Muller C-element based on MOS-NDR

Juan Núñez, Maria J. Avedillo, José M. Quintana, 2009, 2009 IEEE International Symposium on Circuits and Systems.

RTD based logic circuits using generalized threshold gates

Maria J. Avedillo, José M. Quintana, H. Pettenghi, 2008 .

Practical low-cost CPL implementations threshold logic functions

Esther Rodríguez-Villegas, Maria J. Avedillo, Raúl Jiménez, 2001, GLSVLSI '01.

Two-Phase MOBILE Interconnection Schemes for Ultra-Grain Pipeline Applications

Juan Núñez, Maria J. Avedillo, José M. Quintana, 2012, PATMOS.

A threshold logic synthesis tool for RTD circuits

Maria J. Avedillo, José M. Quintana, 2004, Euromicro Symposium on Digital System Design, 2004. DSD 2004..

Reed-Muller descriptions of symmetric functions

Maria J. Avedillo, José M. Quintana, 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).

Optimum PLA folding through boolean satisfiability

José Luis Huertas, Maria J. Avedillo, José M. Quintana, 1995, ASP-DAC '95.

Inverting Versus Non-Inverting Dynamic Logic for Two-Phase Latch-free Nanopipelines

Juan Núñez, Manuel Jimenez, Maria J. Avedillo, 2018, 2018 15th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD).

Robust frequency divider based on resonant tunneling devices

José Luis Huertas, Maria J. Avedillo, José M. Quintana, 2005, 2005 IEEE International Symposium on Circuits and Systems.

A Practical Parallel Architecture for Stacks Filters

Maria J. Avedillo, José M. Quintana, Hamid El Alami, 2004, J. VLSI Signal Process..

Domino inspired MOBILE networks

Maria J. Avedillo, José M. Quintana, Juan Nunez, 2012 .

Constrained state assignment of easily testable FSMs

José Luis Huertas, Maria J. Avedillo, José M. Quintana, 1995, J. Electron. Test..

Synchronisation and chaos in a laser diode driven by a resonant tunnelling diode

Maria J. Avedillo, José M. Quintana, Charles N. Ironside, 2008 .

Multi-threshold threshold logic circuit design using resonant tunnelling devices

Maria J. Avedillo, José M. Quintana, P. M. Kelly, 2003 .