Morihiro Kuga

发表

Accelerated evaluation of SEU failure-in-time using frame-based partial reconfiguration

Masahiro Iida, Motoki Amagasaki, Yoshihiro Ichinomiya, 2012, 2012 International Conference on Field-Programmable Technology.

A logic cell architecture exploiting the shannon expansion for the reduction of configuration memory

Masahiro Iida, Motoki Amagasaki, Morihiro Kuga, 2014, 2014 24th International Conference on Field Programmable Logic and Applications (FPL).

hCODE 2.0: An open-source toolkit for building efficient FPGA-enabled clouds

Masahiro Iida, Motoki Amagasaki, Morihiro Kuga, 2017, 2017 International Conference on Field Programmable Technology (ICFPT).

Tradeoffs in processor design for superscalar architectures

Oubong Gwun, Kazuaki Murakami, Shinji Tomita, 1991 .

A novel states recovery technique for the TMR softcore processor

Tomoyuki Ishida, Motoki Amagasaki, Yoshihiro Ichinomiya, 2009, 2009 International Conference on Field Programmable Logic and Applications.

hCODE: An open-source platform for FPGA accelerators

Masahiro Iida, Motoki Amagasaki, Morihiro Kuga, 2016, 2016 International Conference on Field-Programmable Technology (FPT).

A case study of evaluation technique for soft error tolerance on SRAM-based FPGAs

Motoki Amagasaki, Toshinori Sueyoshi, Morihiro Kuga, 2010, TENCON 2010 - 2010 IEEE Region 10 Conference.

Overview of the JUMP-1, an MPP prototype for general-purpose parallel computations

Hiroshi Nakashima, Hideharu Amano, Hideo Matsuda, 1994, Proceedings of the International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN).

A Feasibility Study for Design Education Using 32bit RISC Microprocessor DLX - FPGA

Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi, 1995 .

Development of a User Interface for FPGA Remote-Reconfiguration Environment

Isao Sakamoto, Morihiro Kuga, Toshinori Sueyoshi, 2004 .

Designing Flexible Reconfigurable Regions to Relocate Partial Bitstreams

Masahiro Iida, Motoki Amagasaki, Yoshihiro Ichinomiya, 2012, 2012 IEEE 20th International Symposium on Field-Programmable Custom Computing Machines.

Blokus Duo engine on a Zynq

Masahiro Iida, Motoki Amagasaki, Morihiro Kuga, 2014, 2014 International Conference on Field-Programmable Technology (FPT).

High-level Synthesis based on Parallel Design Patterns using a Functional Language

Masahiro Iida, Motoki Amagasaki, Morihiro Kuga, 2017, HEART.

3A13 Education program for fundamental engineering design in Kumamoto University : Creative Engineering Design Education program by Soccer Robot Development

Kohichi Ogata, Morihiro Kuga, Makiko Kobayashi, 2015 .

A novel physical defects recovery technique for FPGA-IP cores

Masahiro Iida, Motoki Amagasaki, Morihiro Kuga, 2012, 2012 International Conference on Reconfigurable Computing and FPGAs.

Teaching Materials for System Level Design Education

Toshinori Sueyoshi, Morihiro Kuga, Yasuo Ishii, 2003 .

A Reconfigurable SIMD parallel Processor Utilizing Field Programmable Gate Arrays

Morihiro Kuga, Toshinori Sueyoshi, Ryutaro Mine, 1993 .

A Study of Heterogeneous Computing Design Method based on Virtualization Technology

Masahiro Iida, Motoki Amagasaki, Morihiro Kuga, 2017, CARN.

Improving the soft-error tolerability of a soft-core processor on an FPGA using triple modular redundancy and partial reconfiguration

Masahiro Iida, Motoki Amagasaki, Yoshihiro Ichinomiya, 2011 .

EXPRESS-1: a dynamically reconfigurable platform using embedded processor FPGA

Morihiro Kuga, Toshinori Sueyoshi, Daisuke Uchida, 2004, Proceedings. 2004 IEEE International Conference on Field- Programmable Technology (IEEE Cat. No.04EX921).

Development of FPGA-based Teaching Materials for System Level Design

Toshinori Sueyoshi, Morihiro Kuga, Hiroyuki Yamasaki, 2004 .

Implementation and Evaluation of Remote Logic Analyzer

Morihiro Kuga, Toshinori Sueyoshi, Hideo Harada, 2006 .

FPGA based ASIC Emulator with High Speed Optical Serial Links

Masahiro Iida, Motoki Amagasaki, Morihiro Kuga, 2017, HEART.

Fault Recovery Technique for TMR Softcore Processor System Using Partial Reconfiguration

Masahiro Iida, Motoki Amagasaki, Yoshihiro Ichinomiya, 2012, ICA3PP.

An automatic FPGA design and implementation framework

Masahiro Iida, Motoki Amagasaki, Morihiro Kuga, 2013, 2013 23rd International Conference on Field programmable Logic and Applications.

INSIGHT: an interconnection network simulator for massively parallel computers

Morihiro Kuga, T. Sueyoshi, H. Shibamura, 1994, Proceedings of TENCON'94 - 1994 IEEE Region 10's 9th Annual International Conference on: 'Frontiers of Computer Technology'.

Enabling FPGA-as-a-Service in the Cloud with hCODE Platform

Masahiro Iida, Motoki Amagasaki, Morihiro Kuga, 2018, IEICE Trans. Inf. Syst..

A 3D FPGA Architecture to Realize Simple Die Stacking

Masahiro Iida, Motoki Amagasaki, Morihiro Kuga, 2015, IPSJ Trans. Syst. LSI Des. Methodol..

FPGA Remote-Reconfiguration and Remote Logic Analyzer

Morihiro Kuga, Toshinori Sueyoshi, Hidetomo Shibamura, 2004 .

FPGA Design Framework Combined with Commercial VLSI CAD

Masahiro Iida, Motoki Amagasaki, Morihiro Kuga, 2013, IEICE Trans. Inf. Syst..

Effective Performance Evaluation of High Speed Serial Communication between FPGAs

Morihiro Kuga, Toshinori Sueyoshi, Yuji Ariuchi, 2006 .

A Case Study of Supervisor Processor for Dependable System

Masahiro Iida, Motoki Amagasaki, Yoshihiro Ichinomiya, 2012 .

Physical Fault Detection and Recovery Methods for System-LSI Loaded FPGA-IP Core

Masahiro Iida, Motoki Amagasaki, Morihiro Kuga, 2017, IEICE Trans. Inf. Syst..

Fault detection and avoidance of FPGA in various granularities

Masahiro Iida, Motoki Amagasaki, Morihiro Kuga, 2012, 22nd International Conference on Field Programmable Logic and Applications (FPL).

Parallelization of the channel width search for FPGA routing

Masahiro Iida, Motoki Amagasaki, Morihiro Kuga, 2011, CARN.

KITE microprocessor and CAE for computer science

Morihiro Kuga, Toshinori Sueyoshi, Hidetomo Shibamura, 2002, Systems and Computers in Japan.

Low-cost Hardware that Accelerates Frequent Item Counting with an FPGA

Masahiro Iida, Motoki Amagasaki, Morihiro Kuga, 2017 .

Zyndroid: An Android platform for software/hardware coprocessing

Masahiro Iida, Motoki Amagasaki, Morihiro Kuga, 2014, 2014 International Conference on Field-Programmable Technology (FPT).

A prototype chip of reconfigurable logic device using variable grain logic cell architecture

Masahiro Koga, Masahiro Iida, Motoki Amagasaki, 2010, TENCON 2010 - 2010 IEEE Region 10 Conference.

SIMP (single Instruction Stream/multiple Instruction Pipelining): A Novel High-speed Single-processor Architecture

Kazuaki Murakami, Shinji Tomita, Morihiro Kuga, 1989, The 16th Annual International Symposium on Computer Architecture.

Architecture exploration of 3D FPGA to minimize internal layer connection

Masahiro Iida, Motoki Amagasaki, Morihiro Kuga, 2015, 2015 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC).

FPGA placement based on self-organizing maps

Masahiro Iida, Motoki Amagasaki, Morihiro Kuga, 2015 .

DSNS (dynamically-hazard-resolved statically-code-scheduled, nonuniform superscalar): yet another superscalar processor architecture

Kazuaki Murakami, Shinji Tomita, Morihiro Kuga, 1991, CARN.

Defect-robust FPGA architectures for intellectual property cores in system LSI

Masahiro Iida, Motoki Amagasaki, Morihiro Kuga, 2013, 2013 23rd International Conference on Field programmable Logic and Applications.

A Bitstream Relocation Technique to Improve Flexibility of Partial Reconfiguration

Masahiro Iida, Motoki Amagasaki, Yoshihiro Ichinomiya, 2012, ICA3PP.

Simple wafer stacking 3D-FPGA architecture

Masahiro Iida, Motoki Amagasaki, Morihiro Kuga, 2015, 2015 International Conference on IC Design & Technology (ICICDT).

Fault-Tolerant FPGA: Architectures and Design for Programmable Logic Intellectual Property Core in SoC

Masahiro Iida, Motoki Amagasaki, Morihiro Kuga, 2015, IEICE Trans. Inf. Syst..

Improving the Robustness of a Softcore Processor against SEUs by Using TMR and Partial Reconfiguration

Masahiro Iida, Motoki Amagasaki, Yoshihiro Ichinomiya, 2010, 2010 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines.

A novel FPGA design framework with VLSI post-routing performance analysis (abstract only)

Masahiro Iida, Motoki Amagasaki, Morihiro Kuga, 2013, FPGA '13.

A development scheduling simulater for reconfiguable system

Masahiro Iida, Motoki Amagasaki, Morihiro Kuga, 2012 .

Foreword: Special section on hardware and software technologies on advanced microprocessors

Shorin Kyo, Hiroyuki Tomiyama, Toshinori Sato, 2009 .

Power-aware FPGA routing fabrics and design tools

Masahiro Iida, Motoki Amagasaki, Morihiro Kuga, 2010, 2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip.

Characteristic Similarity Using Classical CNN Model

Motoki Amagasaki, Morihiro Kuga, Mery Diana, 2019, 2019 34th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC).

LC_002 FPGA Remote Reconfiguration and Remote Verification

Morihiro Kuga, Toshinori Sueyoshi, Hideo Harada, 2006 .

Towards Open-HW: A Platform to Design, Share and Deploy FPGA Accelerators in Low Cost

Masahiro Iida, Motoki Amagasaki, Morihiro Kuga, 2017, IPSJ Trans. Syst. LSI Des. Methodol..

A reconfigurable Java accelerator with software compatibility for embedded systems

Yuki Ogawa, Masahiro Iida, Motoki Amagasaki, 2014, CARN.

Memory Sharing Approach for TMR Softcore Processor

Tomoyuki Ishida, Motoki Amagasaki, Yoshihiro Ichinomiya, 2009, ARC.

Evaluation of fault tolerant technique based on homogeneous FPGA architecture

Masahiro Iida, Motoki Amagasaki, Morihiro Kuga, 2012, 2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC).

2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), Darmstadt, Germany, July 10-12, 2013

Leandro Soares Indrusiak, Kartikeya Bhardwaj, Pravin S. Mane, 2013, Reconfigurable Communication-centric Systems-on-Chip.

Fault-Injection Analysis to Estimate SEU Failure in Time by Using Frame-Based Partial Reconfiguration

Masahiro Iida, Motoki Amagasaki, Yoshihiro Ichinomiya, 2012, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Theorem-proving verification for asynchronous circuits

Masahiro Iida, Motoki Amagasaki, Morihiro Kuga, 2016 .

Three-dimensional stacking FPGA architecture using face-to-face integration

Masahiro Iida, Motoki Amagasaki, Morihiro Kuga, 2013, 2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC).

Development of a Run-Time Reconfigurable System using Partially Reconfigurable FPGA

Masahiro Iida, Isao Sakamoto, Morihiro Kuga, 2005 .

An FPGA design and implementation framework combined with commercial VLSI CADs

Masahiro Iida, Motoki Amagasaki, Morihiro Kuga, 2013, 2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC).

An Implementation of Video Streaming Processing on a Dynamically Self-Reconfigurable System

Masahiro Iida, Isao Sakamoto, Morihiro Kuga, 2005 .

Message from DDCPD-12 workshop chairs

Hiroaki Higaki, Kazuaki Tanaka, Andrew Flahive, 2012, UIC 2012.

Automation of Domain-specific FPGA-IP Generation and Test

Motoki Amagasaki, Morihiro Kuga, Qian Zhao, 2021, HEART.