Armaiti Ardeshiricham

Examining the consequences of high-level synthesis optimizations on power side-channel

Wei Hu, Dejun Mu, Lu Zhang, 2018, 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Clepsydra: Modeling timing flows in hardware designs

Wei Hu, Ryan Kastner, Armaiti Ardeshiricham, 2017, 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Identifying and Measuring Security Critical Path for Uncovering Circuit Vulnerabilities

Wei Hu, Ryan Kastner, Armaiti Ardeshiricham, 2017, 2017 18th International Workshop on Microprocessor and SOC Test and Verification (MTV).

Why you should care about don't cares: Exploiting internal don't care conditions for hardware Trojans

Wei Hu, Lu Zhang, Ryan Kastner, 2017, 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Verification and Synthesis of Information Flow Secure Hardware Designs

Armaiti Ardeshiricham, 2020 .

Register transfer level information flow tracking for provably secure hardware design

Wei Hu, Ryan Kastner, Armaiti Ardeshiricham, 2017, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017.

A Unified Model for Gate Level Propagation Analysis pdf

Wei Hu, Armaiti Ardeshiricham, Jeremy Blackstone, 2020, ArXiv.

Property Specific Information Flow Analysis for Hardware Security Verification

Wei Hu, Ryan Kastner, Armaiti Ardeshiricham, 2018, 2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

VeriSketch: Synthesizing Secure Hardware Designs with Timing-Sensitive Information Flow Properties

Sicun Gao, Armaiti Ardeshiricham, Ryan Kastner, 2019, CCS.

Hardware Information Flow Tracking

Wei Hu, Ryan Kastner, Armaiti Ardeshiricham, 2021, ACM Comput. Surv..