W.H. Lee

A 90nm generation NOR flash multilevel cell (MLC) with 0.44/spl mu/m/sup 2//bit cell size

Wook Hyun Kwon, Kyung Tae Kim, Kinam Kim, 2005, IEEE VLSI-TSA International Symposium on VLSI Technology, 2005. (VLSI-TSA-Tech)..

Design and Image Processing of Novel Diffractive Optical Modulator for Embedded Mobile Display Applications

S.J. Lee, C.S. Park, J.H. Kim, 2007, 2007 Conference on Lasers and Electro-Optics - Pacific Rim.

Fully 3-Dimensional NOR Flash Cell with Recessed Channel and Cylindrical Floating Gate - A Scaling Direction for 65nm and Beyond

Kinam Kim, Kwang Soo Kim, Sang-Pil Sim, 2006, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..

A high performance 90nm SOI technology with 0.992 /spl mu/m2 6T-SRAM cell

S. Narasimha, A. Gabor, W. Rausch, 2002, Digest. International Electron Devices Meeting,.

Temperature Dependence of Endurance Characteristics in NOR Flash Memory Cells

Kinam Kim, W.H. Lee, Chan-Kwang Park, 2006, 2006 IEEE International Reliability Physics Symposium Proceedings.

Impact of floating gate dry etching on erase characteristics in NOR flash memory

Kang-Deog Suh, Yonghan Roh, W.H. Lee, 2002, IEEE Electron Device Letters.

Gate quality doped high K films for CMOS beyond 100 nm: 3-10 nm Al/sub 2/O/sub 3/ with low leakage and low interface states

M.D. Morris, P.J. Silverman, W.H. Lee, 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).