Yong-Hun Kim

发表

A 10.8 Gb/s Quarter-Rate 1 FIR 1 IIR Direct DFE With Non-Time-Overlapping Data Generation for 4:1 CMOS Clockless Multiplexer

Lee-Sup Kim, Hyun-Kyu Jeon, Daewoong Lee, 2020, IEEE Transactions on Circuits and Systems II: Express Briefs.

A 0.9-V 12-Gb/s Two-FIR Tap Direct DFE With Feedback-Signal Common-Mode Control

Lee-Sup Kim, Yong-Hun Kim, Dongil Lee, 2019, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

An injection locked PLL for power supply variation robustness using negative phase shift phenomenon of injection locked frequency divider

Lee-Sup Kim, Yong-Hun Kim, Dongil Lee, 2015, 2015 IEEE Custom Integrated Circuits Conference (CICC).

A 20 Gbps 1-tap decision feedback equalizer with unfixed tap coefficient

Lee-Sup Kim, Yong-Hun Kim, 2012, 2012 IEEE International Symposium on Circuits and Systems.

An 8Gb/s 1-tap Feed Forward Equalizer and 1-tap Decision Feed Forward Equalizer in 65㎚ CMOS

Lee-Sup Kim, Yong-Hun Kim, 2012 .

A Postfiltering Algorithm for Enhancement in Block-based DCT Compressed Images

Yong-Hun Kim, Jong-Hyeog Jeong, 2014 .

(An) input data and clock jitter tolerant digital CDR for LCD intra-panel interface = LCD 인트라패널 인터페이스에서 데이터와 클락 지터에 강인한 디지털 클락 및 데이터 복원 회로

Yong-Hun Kim, 2017 .

Color Inverse Halftoning using Vector Adaptive Filter

Yong-Hun Kim, Chan-Su Kim, Tai-Hong Yi, 2008 .

A 10-Gb/s 0.71-pJ/bit Forwarded-Clock Receiver Tolerant to High-Frequency Jitter in 65-nm CMOS

Lee-Sup Kim, Yong-Hun Kim, Young-Ju Kim, 2016, IEEE Transactions on Circuits and Systems II: Express Briefs.

An integrated time register and arithmetic circuit with combined operation for time-domain signal processing

Lee-Sup Kim, Yong-Hun Kim, Dongil Lee, 2015, 2015 IEEE International Symposium on Circuits and Systems (ISCAS).

Smart card based three party key exchange protocol without server's aid

Young-Ho Park, Yong-Hun Kim, Taek-Young Youn, 2008 .

A New Unbiased Symbol Synchronization Loop Using Fixed Clock And Non-ideal Interpolator

Kyung-Ha Lee, Hyung-Jin Choi, Yong-Hun Kim, 1997 .

An Input Data and Power Noise Inducing Clock Jitter Tolerant Reference-Less Digital CDR for LCD Intra-Panel Interface

Lee-Sup Kim, Hyun-Kyu Jeon, Yong-Hun Kim, 2017, IEEE Transactions on Circuits and Systems I: Regular Papers.

A CMOS LC-tank VCO and phase shifting network for direct conversion receiver of IEEE 802.11a

Changsik Yoo, Chan-Young Jeong, Mi-Young Lee, 2005 .

A 16-Gb, 18-Gb/s/pin GDDR6 DRAM With Per-Bit Trainable Single-Ended DFE and PLL-Less Clocking

Hyun-Soo Park, Hyuk-Jun Kwon, Kyungbae Park, 2019, IEEE Journal of Solid-State Circuits.

A 21-Gbit/s 1.63-pJ/bit Adaptive CTLE and One-Tap DFE With Single Loop Spectrum Balancing Method

Lee-Sup Kim, Yong-Hun Kim, Young-Ju Kim, 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A 5-Gb/s 2.67-mW/Gb/s Digital Clock and Data Recovery With Hybrid Dithering Using a Time-Dithered Delta–Sigma Modulator

Jun-Seok Park, Lee-Sup Kim, Yong-Hun Kim, 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A 0.65-V, 11.2-Gb/s Power Noise Tolerant Source-Synchronous Injection-Locked Receiver With Direct DTLB DFE

Lee-Sup Kim, Yong-Hun Kim, Dongil Lee, 2018, IEEE Transactions on Circuits and Systems II: Express Briefs.

Iterative Image Restoration using Adaptive Directional Regularization

Yong-Hun Kim, Hyoun-Jin Shin, Tai-Hong Yi, 2006 .

A CMOS Quadrature Down-Converter for Direct-Conversion Receiver of 5.15-5.825GHz Wireless LAN

Changsik Yoo, Kwang-Soon Kim, Jin-Hong Hwang, 2005 .

A 10-Gb/s Reference-Less Baud-Rate CDR for Low Power Consumption With the Direct Feedback Method

Lee-Sup Kim, Yong-Hun Kim, Dongil Lee, 2018, IEEE Transactions on Circuits and Systems II: Express Briefs.

USING FIXED CLOCK AND NON-IDEAL INTERPOLATOR

Kyung-Ha Lee, Hyung-Jin Choi, Yong-Hun Kim, 1997 .

Dictionary attack of remote user authentication scheme using side channel analysis

Yong-Hun Kim, Taek-Young Youn, Young-Ho Park, 2008 .

A 12 Gb/s 1.59 mW/Gb/s Input-Data-Jitter-Tolerant Injection-Type CDR With Super-Harmonic Injection-Locking in 65-nm CMOS

Lee-Sup Kim, Daewoong Lee, Dongil Lee, 2019, IEEE Transactions on Circuits and Systems II: Express Briefs.

A 16Gb 18Gb/S/pin GDDR6 DRAM with per-bit trainable single-ended DFE and PLL-less clocking

Yong Jae Lee, Hyun-Soo Park, Hyuk-Jun Kwon, 2018, 2018 IEEE International Solid - State Circuits Conference - (ISSCC).

A 5-Gb/s Digital Clock and Data Recovery Circuit With Reduced DCO Supply Noise Sensitivity Utilizing Coupling Network

Lee-Sup Kim, Yong-Hun Kim, Taeho Lee, 2017, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

웹 얼굴 사진의 실시간 추출 및 합성을 통한 전체적 얼굴 = A collective face through realtime analysis and synthesis of facial photos on the web

김용훈, Yong-Hun Kim, Yong-Hun Kim, 2012 .

An 11.5 Gb/s 1/4th Baud-Rate CTLE and Two-Tap DFE With Boosted High Frequency Gain in 110-nm CMOS

Lee-Sup Kim, Yong-Hun Kim, Young-Ju Kim, 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

25.2 A 16Gb Sub-1V 7.14Gb/s/pin LPDDR5 SDRAM Applying a Mosaic Architecture with a Short-Feedback 1-Tap DFE, an FSS Bus with Low-Level Swing and an Adaptively Controlled Body Biasing in a 3rd-Generation 10nm DRAM

Reum Oh, Byongwook Na, Jeong-Don Ihm, 2021, 2021 IEEE International Solid- State Circuits Conference (ISSCC).