Xiaowei Li

发表

A unified test architecture for on-line and off-line delay fault detections

Songwei Pei, Huawei Li, Xiaowei Li, 2011, 29th VLSI Test Symposium.

Test Path Selection for Capturing Delay Failures Under Statistical Timing Model

Huawei Li, Xiaowei Li, Zijian He, 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Oware: Operand width Aware Redundant Execution for Whole-Processor Error Detection

Xiaowei Li, Zhongliang Chen, Yu Hu, 2011, Intell. Autom. Soft Comput..

Leveraging FVT-margins in design space exploration for FFGA-based CNN accelerators

Yu Hu, Xiaowei Li, Jing Ye, 2017, 2017 27th International Conference on Field Programmable Logic and Applications (FPL).

A Scan-Based Delay Test Method for Reduction of Overtesting

Yu Hu, Hui Liu, Huawei Li, 2008, 4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008).

Testable Critical Path Selection Considering Process Variation

Huawei Li, Xiaowei Li, Xiang Fu, 2010, IEICE Trans. Inf. Syst..

Deterministic and low power BIST based on scan slice overlapping

Xiaowei Li, Ji Li, Yinhe Han, 2005, 2005 IEEE International Symposium on Circuits and Systems.

On predicting NBTI-induced circuit aging by isolating leakage change

Qiang Xu, Xiaowei Li, Song Jin, 2013, International Symposium on Quality Electronic Design (ISQED).

A unified architecture for speed-binning and circuit failure prediction and detection

Songwei Pei, Huawei Li, Xiaowei Li, 2012, 2012 IEEE International Conference on Computer Science and Automation Engineering (CSAE).

An Efficient Algorithm for Finding a Universal Set of Testable Long Paths

Huawei Li, Xiaowei Li, Zijian He, 2010, 2010 19th IEEE Asian Test Symposium.

Response compaction for system-on-a-chip based on advanced convolutional codes

Huawei Li, Xiaowei Li, Yinhe Han, 2006, Science in China Series F: Information Sciences.

P3M: a PIM-based neural network model protection scheme for deep learning accelerator

Ying Wang, Huawei Li, Xiaowei Li, 2019, ASP-DAC.

A New Multiple-Round Dimension-Order Routing for Networks-on-Chip

Huawei Li, Xiaowei Li, Yinhe Han, 2011, IEICE Trans. Inf. Syst..

Capture-power-aware test data compression using selective encoding

Yu Hu, Qiang Xu, Xiaowei Li, 2011, Integr..

Multiple Coupling Effects Oriented Path Delay Test Generation

Huawei Li, Xiaowei Li, Minjin Zhang, 2008, 26th IEEE VLSI Test Symposium (vts 2008).

Performance-asymmetry-aware topology virtualization for defect-tolerant NoC-based many-core processors

Xiaowei Li, Yue Yu, Shangping Ren, 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

Formal Verification Techniques Based on Boolean Satisfiability Problem

Xiaowei Li, Ming Shao, Guanghui Li, 2005, Journal of Computer Science and Technology.

iFill: An Impact-Oriented X-Filling Method for Shift- and Capture-Power Reduction in At-Speed Scan-Based Testing

Yu Hu, Qiang Xu, Xiaowei Li, 2008, 2008 Design, Automation and Test in Europe.

Enabling Near-Threshold Voltage(NTV) operation in Multi-VDD cache for power reduction

Huawei Li, Xiaowei Li, Yinhe Han, 2013, 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013).

HARS: A High-Performance Reliable Routing Scheme for 3D NoCs

Jun Zhou, Huawei Li, Xiaowei Li, 2014, 2014 IEEE Computer Society Annual Symposium on VLSI.

Design-for-Testability Features and Test Implementation of a Giga Hertz General Purpose Microprocessor

Yu Hu, Huawei Li, Xiaowei Li, 2008, Journal of Computer Science and Technology.

High-level BIST synthesis for delay testing

Xiaowei Li, Paul Y. S. Cheung, 1998, Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223).

Validation analysis and test flow optimization of VLSI chip

Xiaowei Li, Yinhe Han, Yanzhuo Tan, 2005, 2005 IEEE International Symposium on Circuits and Systems.

Time Synchronization Simulator and Its Application

Xiaowei Li, Lei Zhao, Yongjun Xu, 2006, 2006 1ST IEEE Conference on Industrial Electronics and Applications.

Energy-Aware QoS Control for Wireless Sensor Network

Xiaowei Li, Lei Zhao, Yongjun Xu, 2006, 2006 1ST IEEE Conference on Industrial Electronics and Applications.

SNAMP: A Multi-sniffer and Multi-view Visualization Platform for Wireless Sensor Networks

Xiaowei Li, Quan Zhou, Yongjun Xu, 2006, 2006 1ST IEEE Conference on Industrial Electronics and Applications.

Frequency Analysis Method for Propagation of Transient Errors in Combinational Logic

Xiaowei Li, Yinhe Han, Shaohua Lei, 2007, 16th Asian Test Symposium (ATS 2007).

CNN-based object detection solutions for embedded heterogeneous multicore SoCs

Cheng Wang, Xiaowei Li, Yinhe Han, 2017, 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC).

Graph partition based path selection for testing of small delay defects

Huawei Li, Xiaowei Li, Zijian He, 2010, 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC).

Path Delay Test Generation Toward Activation of Worst Case Coupling Effects

Huawei Li, Xiaowei Li, Minjin Zhang, 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Data path synthesis for BIST with low area overhead

Xiaowei Li, Paul Y. S. Cheung, 1999, Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198).

SmartCap: User experience-oriented power adaptation for smartphone's application processor

Xiaowei Li, Yinhe Han, Xueliang Li, 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

PUFPass: A password management mechanism based on software/hardware codesign

Yu Hu, Xiaowei Li, Jing Ye, 2019, Integr..

An abstraction-guided simulation approach using Markov models for microprocessor verification

Tao Zhang, Xiaowei Li, Tao Lv, 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

Simultaneous Reduction of Test Data Volume and Testing Power for Scan-Based Test

Xiaowei Li, Yinhe Han, 2004, ESA/VLSI.

Adaptive Diagnostic Pattern Generation for Scan Chains

Yu Hu, Fei Wang, Xiaowei Li, 2008, 4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008).

Hierarchical fault tolerance memory architecture with 3-dimension interconnect

Huawei Li, Xiaowei Li, Yu Hu, 2007, TENCON 2007 - 2007 IEEE Region 10 Conference.

A clustering-based scheme for concurrent trace in debugging NoC-based multicore systems

Xiaowei Li, Jianxin Wang, Yinhe Han, 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).

P^(2)CLRAF: An Pre- and Post-Silicon Cooperated Circuit Lifetime Reliability Analysis Framework

Huawei Li, Xiaowei Li, Song Jin, 2010, 2010 19th IEEE Asian Test Symposium.

An innovative free memory design for network processors in home network gateway

Huawei Li, Xiaowei Li, Shuguang Gong, 2005, IEEE Transactions on Consumer Electronics.

A High-Precision On-Chip Path Delay Measurement Architecture

Songwei Pei, Huawei Li, Xiaowei Li, 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

CoreRank: Redeeming “Sick Silicon” by Dynamically Quantifying Core-Level Healthy Condition

Huawei Li, Xiaowei Li, Guihai Yan, 2016, IEEE Transactions on Computers.

Real-time meets approximate computing: An elastic CNN inference accelerator with adaptive trade-off between QoS and QoR

Huawei Li, Xiaowei Li, Ying Wang, 2017, 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC).

Delay test pattern generation considering crosstalk-induced effects

Yue Zhang, Huawei Li, Xiaowei Li, 2003, 2003 Test Symposium.

Test resource partitioning based on efficient response compaction for test time and tester channels reduction

Huawei Li, Xiaowei Li, Yongjun Xu, 2003, 2003 Test Symposium.

SAT-based algorithm of verification for port order fault

Xiaowei Li, Ming Shao, Guanghui Li, 2003, 2003 Test Symposium.

Short-SET: An energy-efficient write scheme for MLC PCM

Yu Hu, Xiaowei Li, Bing Li, 2014, 2014 IEEE Non-Volatile Memory Systems and Applications Symposium (NVMSA).

Defect Tolerance in Homogeneous Manycore Processors Using Core-Level Redundancy with Unified Topology

Qiang Xu, Xiaowei Li, Yinhe Han, 2008, 2008 Design, Automation and Test in Europe.

High level synthesis for loop-based BIST

Xiaowei Li, Paul Y. S. Cheung, P. Cheung, 2000, Journal of Computer Science and Technology.

Fault diagnosis of arbiter physical unclonable function

Yu Hu, Xiaowei Li, Jing Ye, 2017, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017.

Bug analysis and corresponding error models in real designs

Huawei Li, Xiaowei Li, Yang Zhao, 2007, 2007 IEEE International High Level Design Validation and Test Workshop.

Fault tolerance on-chip: a reliable computing paradigm using self-test, self-diagnosis, and self-repair (3S) approach

Xiaowei Li, Ying Wang, Jing Ye, 2018, Science China Information Sciences.

A Fault Criticality Evaluation Framework of Digital Systems for Error Tolerant Video Applications

Huawei Li, Xiaowei Li, Yuntan Fang, 2011, 2011 Asian Test Symposium.

Property Coverage Analysis Based Trustworthiness Verification for Potential Threats from EDA Tools

Huawei Li, Xiaowei Li, Yingxin Qiu, 2016, 2016 IEEE 25th Asian Test Symposium (ATS).

Automatic Selection of Internal Observation Signals for Design Verification

Huawei Li, Xiaowei Li, Tao Lv, 2009, 2009 27th IEEE VLSI Test Symposium.

Efficient Attack on Non-linear Current Mirror PUF with Genetic Algorithm

Yu Hu, Xiaowei Li, Jing Ye, 2016, 2016 IEEE 25th Asian Test Symposium (ATS).

A novel RTL behavioral description based ATPG method

Huawei Li, Xiaowei Li, Yinghua Min, 2008, Journal of Computer Science and Technology.

Nonidentical Linear Pulse-Coupled Oscillators Model With Application to Time Synchronization in Wireless Sensor Networks

Xiaowei Li, Hongsong Zhu, Yongjun Xu, 2011, IEEE Transactions on Industrial Electronics.

Functional Test Generation for Hard-to-Reach States Using Path Constraint Solving

Huawei Li, Xiaowei Li, Yanhong Zhou, 2016, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A Lightweight Timing Channel Protection for Shared Memory Controllers

Huawei Li, Xiaowei Li, Sen Li, 2015, 2015 IEEE 24th Asian Test Symposium (ATS).

3D Segmentation of Mice Gland Based on Ensemble Learning

Xiaowei Li, Min Li, Dongming Yang, 2019, 2019 12th International Congress on Image and Signal Processing, BioMedical Engineering and Informatics (CISP-BMEI).

Wrapper Scan Chains Design for Rapid and Low Power Testing of Embedded Cores

Yu Hu, Huawei Li, Xiaowei Li, 2005, IEICE Trans. Inf. Syst..

LOFT: A low-overhead fault-tolerant routing scheme for 3D NoCs

Jun Zhou, Huawei Li, Xiaowei Li, 2016, Integr..

On-Chip Delay Sensor for Environments with Large Temperature Fluctuations

Xiaowei Li, Jibing Qiu, Guihai Yan, 2014, 2014 IEEE 23rd Asian Test Symposium.

An Efficient Evaluation and Vector Generation Method for Observability-Enhanced Statement Coverage

Xiaowei Li, Wei Lu, Tao Lv, 2005, Journal of Computer Science and Technology.

On capture power-aware test data compression for scan-based testing

Yu Hu, Qiang Xu, Xiaowei Li, 2008, 2008 IEEE/ACM International Conference on Computer-Aided Design.

Diagnosis of multiple arbitrary faults with mask and reinforcement effect

Yu Hu, Xiaowei Li, Jing Ye, 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

Test Generation for Crosstalk Glitches Considering Multiple Coupling Effects

Xiaowei Li, Minjin Zhang, 2007, 16th Asian Test Symposium (ATS 2007).

Reducing power dissipation during at-speed test application

Huawei Li, Xiaowei Li, Yinghua Min, 2001, Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

Exploiting BIST approach for two-pattern testing

Xiaowei Li, Paul Y. S. Cheung, 1998, Proceedings Seventh Asian Test Symposium (ATS'98) (Cat. No.98TB100259).

Robust test generation for precise crosstalk-induced path delay faults

Huawei Li, Xiaowei Li, Pei-Fu Shen, 2006, 24th IEEE VLSI Test Symposium.

A resilient on-chip router design through data path salvaging

Xiaowei Li, Yinhe Han, Cheng Liu, 2011, 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011).

Reliable Network-on-Chip Router for Crosstalk and Soft Error Tolerance

Ying Zhang, Huawei Li, Xiaowei Li, 2008, 2008 17th Asian Test Symposium.

FlexFlow: A Flexible Dataflow Accelerator Architecture for Convolutional Neural Networks

Xiaowei Li, Yinhe Han, Jiajun Li, 2017, 2017 IEEE International Symposium on High Performance Computer Architecture (HPCA).

An Analytical Framework for Estimating Scale-Out and Scale-Up Power Efficiency of Heterogeneous Manycores

Xiaowei Li, Jun Ma, Yinhe Han, 2016, IEEE Transactions on Computers.

A Security Mechanism For RFID With Dependable Proxy

Jun Zhou, Xiaowei Li, Yongjun Xu, 2011, Intell. Autom. Soft Comput..

SoftPCM: Enhancing Energy Efficiency and Lifetime of Phase Change Memory in Video Applications via Approximate Write

Huawei Li, Xiaowei Li, Yuntan Fang, 2012, 2012 IEEE 21st Asian Test Symposium.

Orchestrator: A low-cost solution to reduce voltage emergencies for multi-threaded applications

Yu Hu, Xiaowei Li, Xing Hu, 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Abstraction-Guided Simulation Using Markov Analysis for Functional Verification

Jian Wang, Huawei Li, Xiaowei Li, 2016, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Exploiting the Potential of Computation Reuse Through Approximate Computing

Xin He, Xiaowei Li, Yinhe Han, 2017, IEEE Transactions on Multi-Scale Computing Systems.

Tolerating Noise in MLC PCM with Multi-Bit Error Correction Code

Yu Hu, Xiaowei Li, Bing Li, 2013, 2013 IEEE 19th Pacific Rim International Symposium on Dependable Computing.

Address Remapping for Static NUCA in NoC-Based Degradable Chip-Multiprocessors

Huawei Li, Xiaowei Li, Yinhe Han, 2010, 2010 IEEE 16th Pacific Rim International Symposium on Dependable Computing.

A Case Study on At-Speed Testing for a Gigahertz Microprocessor

Yu Hu, Huawei Li, Xiaowei Li, 2008, 4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008).

Power-Utility-Driven Write Management for MLC PCM

Yu Hu, Xiaowei Li, Jing Ye, 2017, ACM J. Emerg. Technol. Comput. Syst..

An efficient observability evaluation algorithm based on Factored Use-Def chains

Xiaowei Li, Tao Lv, Jianping Fan, 2003, 2003 Test Symposium.

ApproxEye: Enabling approximate computation reuse for microrobotic computer vision

Xin He, Xiaowei Li, Yinhe Han, 2017, 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC).

Selected Transition Time Adjustment for Tolerating Crosstalk Effects on Network-on-Chip Interconnects

Ying Zhang, Huawei Li, Xiaowei Li, 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

On diagnosis of multiple faults using compacted responses

Yu Hu, Xiaowei Li, Jing Ye, 2011, 2011 Design, Automation & Test in Europe.

Codeword Selection for Crosstalk Avoidance and Error Correction on Interconnects

Yu Hu, Ying Zhang, Huawei Li, 2008, 26th IEEE VLSI Test Symposium (vts 2008).

Computer simulation of photosensitive process of image materials

Xiaowei Li, Lianshui Zhang, Xiaoyong Hu, 2001, International Symposium on Multispectral Image Processing and Pattern Recognition.

A Novel Post-Silicon Debug Mechanism Based on Suspect Window

Xiaowei Li, Yinhe Han, Jianliang Gao, 2010, IEICE Trans. Inf. Syst..

Eliminating data invalidation in debugging multiple-clock chips

Xiaowei Li, Yinhe Han, Jianliang Gao, 2011, 2011 Design, Automation & Test in Europe.

A greedy approach to tolerate defect cores for multimedia applications

Xiaowei Li, Shangping Ren, Zheng Li, 2011, 2011 9th IEEE Symposium on Embedded Systems for Real-Time Multimedia.

A State Machine for Detecting C/C++ Memory Faults

Guangyan Huang, Yunzhan Gong, Xiaowei Li, 2005, 14th Asian Test Symposium (ATS'05).

Re-architecting the on-chip memory sub-system of machine-learning accelerator for embedded devices

Huawei Li, Xiaowei Li, Ying Wang, 2016, 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Frequency scheduling for resilient chip multi-processors operating at Near Threshold Voltage

Huawei Li, Xiaowei Li, Ying Wang, 2016, 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Economizing TSV Resources in 3-D Network-on-Chip Design

Lei Zhang, Huawei Li, Xiaowei Li, 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A Loss Inference Algorithm for Wireless Sensor Networks to Improve Data Reliability of Digital Ecosystems

Xiaowei Li, Yu Yang, Yongjun Xu, 2011, IEEE Transactions on Industrial Electronics.

Response compaction for test time and test pins reduction based on advanced convolutional codes

Yu Hu, Huawei Li, Xiaowei Li, 2004, 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2004. DFT 2004. Proceedings..

Flex memory: Exploiting and managing abundant off-chip optical bandwidth

Huawei Li, Xiaowei Li, Yinhe Han, 2011, 2011 Design, Automation & Test in Europe.

Deterministic circular self test path

Yu Hu, Xiaowei Li, Ke Wen, 2007 .

Scan chain design for shift power reduction in scan-based testing

Yu Hu, Xiaowei Li, Jia Li, 2011, Science China Information Sciences.

Wavelet-based iterative perfect reconstruction in computational integral imaging.

Xiaowei Li, Qiong-Hua Wang, Lei Li, 2018, Journal of the Optical Society of America. A, Optics, image science, and vision.

BAT: Performance-Driven Crosstalk Mitigation Based on Bus-Grouping Asynchronous Transmission

Hui Liu, Xiaowei Li, Yinhe Han, 2008, IEICE Trans. Electron..

In-Field Testing of NAND Flash Storage: Why and How?

Yu Hu, Xiaowei Li, Xinli Gu, 2012, 2012 IEEE 21st Asian Test Symposium.

An approach to behavioral synthesis for loop-based BIST

Xiaowei Li, Paul Y. S. Cheung, 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).

Diagnose Failures Caused by Multiple Locations at a Time

Yu Huang, Yu Hu, Xiaowei Li, 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

The Identification of Green Tea Based on Feature Extraction

Xiaowei Li, Guang Li, Xiao Hui Zhao, 2013 .

Average leakage current macromodeling for dual-threshold voltage circuits

Xiaowei Li, Zuying Luo, Yongjun Xu, 2003, 2003 Test Symposium.

Bias PUF based Secure Scan Chain Design

Yu Hu, Huawei Li, Xiaowei Li, 2018, 2018 Asian Hardware Oriented Security and Trust Symposium (AsianHOST).

RSAK: Random stream attack for phase change memory in video applications

Huawei Li, Xiaowei Li, Yuntan Fang, 2013, 2013 IEEE 31st VLSI Test Symposium (VTS).

Wear rate leveling: Lifetime enhancement of PRAM with endurance variation

Xiaowei Li, Yinhe Han, Ying Wang, 2011, 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC).

Lightweight Timing Channel Protection for Shared DRAM Controller

Ying Wang, Huawei Li, Xiaowei Li, 2018, 2018 IEEE International Test Conference (ITC).

Accelerating Lightpath setup via broadcasting in binary-tree waveguide in Optical NoCs

Huawei Li, Xiaowei Li, Yinhe Han, 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

Flip-Flop Selection for Partial Enhanced Scan to Reduce Transition Test Data Volume

Songwei Pei, Huawei Li, Xiaowei Li, 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A unified online Fault Detection scheme via checking of Stability Violation

Xiaowei Li, Yinhe Han, Guihai Yan, 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

Dadu: Accelerating Inverse Kinematics for high-DOF robots

Xiaowei Li, Ninghui Sun, Yinhe Han, 2017, 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC).

Leakage Current Optimization Techniques During Test Based on Don’t Care Bits Assignment

Wei Wang, Xiaowei Li, Yu Hu, 2007, Journal of Computer Science and Technology.

Online Computing and Predicting Architectural Vulnerability Factor of Microprocessor Structures

Yu Hu, Xiaowei Li, Songjun Pan, 2009, 2009 15th IEEE Pacific Rim International Symposium on Dependable Computing.

A Novel Localization Scheme Based on RSS Data for Wireless Sensor Networks

Xiaowei Li, Hongyang Chen, Ping Deng, 2006, APWeb Workshops.

Exploiting Free LUT Entries to Mitigate Soft Errors in SRAM-based FPGAs

Yu Hu, Xiaowei Li, Hongjin Liu, 2011, 2011 Asian Test Symposium.

Diagnosis of Mask-Effect Multiple Timing Faults in Scan Chains

Yu Hu, Fei Wang, Xiaowei Li, 2008, 2008 IEEE International Test Conference.

An estimation method for the parameters of elliptic cone surface

Xiaowei Li, Xiaoyu Chen, Zhengwei Qu, 2018, 2018 IEEE International Instrumentation and Measurement Technology Conference (I2MTC).

A loop-based apparatus for at-speed self-testing

Xiaowei Li, Paul Y. S. Cheung, P. Cheung, 2001, Journal of Computer Science and Technology.

Test-Quality Optimization for Variable $n$ -Detections of Transition Faults

Huawei Li, Xiaowei Li, Kwang-Ting Cheng, 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Wrapper Chain Design for Testing TSVs Minimization in Circuit-Partitioned 3D SoC

Xiaowei Li, Jun Liu, Yinhe Han, 2011, 2011 Asian Test Symposium.

Capturing post-silicon variation by layout-aware path-delay testing

Yu Hu, Xiaowei Li, Jing Ye, 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

C-Brain: A deep learning accelerator that tames the diversity of CNNs through adaptive data-level parallelization

Xiaowei Li, Xin Zhao, Yinhe Han, 2016, 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC).

VANUCA: Enabling Near-Threshold Voltage Operation in Large-Capacity Cache

Huawei Li, Xiaowei Li, Yinhe Han, 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

An on-chip combinational decompressor for reducing test data volume

Yu Hu, Xiaowei Li, Yinhe Han, 2006, 2006 IEEE International Symposium on Circuits and Systems.

A Low Overhead On-Chip Path Delay Measurement Circuit

Songwei Pei, Huawei Li, Xiaowei Li, 2009, 2009 Asian Test Symposium.

ApproxPIM: Exploiting realistic 3D-stacked DRAM for energy-efficient processing in-memory

Huawei Li, Xiaowei Li, Yibin Tang, 2017, 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC).

RISO: Relaxed network-on-chip isolation for cloud processors

Xiaowei Li, Yinhe Han, Binzhang Fu, 2013, 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC).

Pair balance-based test scheduling for SOCs

Yu Hu, Huawei Li, Xiaowei Li, 2004, 13th Asian Test Symposium.

A case of precision-tunable STT-RAM memory design for approximate neural network

Huawei Li, Xiaowei Li, Yinhe Han, 2015, 2015 IEEE International Symposium on Circuits and Systems (ISCAS).

Selective off-loading to Memory: Task Partitioning and Mapping for PIM-enabled Heterogeneous Systems

Huawei Li, Xiaowei Li, Yi Liao, 2017, Conf. Computing Frontiers.

Software-Based Self-Testing of Processors Using Expanded Instructions

Ying Zhang, Huawei Li, Xiaowei Li, 2010, 2010 19th IEEE Asian Test Symposium.

X-Filling for Simultaneous Shift- and Capture-Power Reduction in At-Speed Scan-Based Testing

Yu Hu, Qiang Xu, Xiaowei Li, 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

nGFSIM : A GPU-based fault simulator for 1-to-n detection and its applications

Huawei Li, Xiaowei Li, Kwang-Ting Cheng, 2010, 2010 IEEE International Test Conference.

Rapid and energy-efficient testing for embedded cores

Yu Hu, Huawei Li, Xiaowei Li, 2004, 13th Asian Test Symposium.

Static Crosstalk Noise Analysis with Transition Map

Huawei Li, Xiaowei Li, Minjin Zhang, 2008, 4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008).

Diagnosis and Layout Aware (DLA) Scan Chain Stitching

Yu Hu, Xiaowei Li, Jing Ye, 2015, IEEE Trans. Very Large Scale Integr. Syst..

Selected Crosstalk Avoidance Code for Reliable Network-on-Chip

Ying Zhang, Huawei Li, Xiaowei Li, 2009, Journal of Computer Science and Technology.

A New Post-Silicon Debug Approach Based on Suspect Window

Xiaowei Li, Yinhe Han, Jianliang Gao, 2009, 2009 27th IEEE VLSI Test Symposium.

SVFD: A Versatile Online Fault Detection Scheme via Checking of Stability Violation

Xiaowei Li, Yinhe Han, Guihai Yan, 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Fast algorithm for leakage power reduction by input vector control

Dongrui Fan, Xiaowei Li, Yinhe Han, 2005, 2005 6th International Conference on ASIC.

An approach to RTL fault extraction and test generation

Xiaowei Li, Yinghua Min, Zhigang Yin, 2001, Proceedings 10th Asian Test Symposium.

HTSMAC: High Throughput Sensor MAC for Wireless Video Networks

Xiaowei Li, Quan Zhou, Yongjun Xu, 2007, 2007 International Conference on Wireless Communications, Networking and Mobile Computing.

RISO: Enforce Noninterfered Performance With Relaxed Network-on-Chip Isolation in Many-Core Cloud Processors

Xiaowei Li, Yinhe Han, Ying Wang, 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

TWiN: A Turn-Guided Reliable Routing Scheme for Wireless 3D NoCs

Jun Zhou, Huawei Li, Xiaowei Li, 2015, 2015 IEEE 24th Asian Test Symposium (ATS).

PSI Conscious Write Scheduling: Architectural Support for Reliable Power Delivery in 3-D Die-Stacked PCM

Lei Zhang, Huawei Li, Xiaowei Li, 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Cross-layer optimized placement and routing for FPGA soft error mitigation

Yu Hu, Xiaowei Li, Keheng Huang, 2011, 2011 Design, Automation & Test in Europe.

ProPRAM: Exploiting the transparent logic resources in Non-Volatile Memory for Near Data Computing

Huawei Li, Xiaowei Li, Yinhe Han, 2015, 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC).

Analysis of Forwarding Mechanisms on Fine-Grain Gradient Sinking Model in WSN

Xiaowei Li, Yi Sun, Limin Sun, 2008, J. Signal Process. Syst..

Transparent dynamic binding with fault-tolerant cache coherence protocol for chip multiprocessors

Yu Hu, Xiaowei Li, Shuchang Shan, 2011, 2011 IEEE/IFIP 41st International Conference on Dependable Systems & Networks (DSN).

Flip-flop clustering based trace signal selection for post-silicon debug

Huawei Li, Xiaowei Li, Bo Liu, 2017, 2017 IEEE 35th VLSI Test Symposium (VTS).

Reliability-Oriented Placement and Routing Algorithm for SRAM-Based FPGAs

Yu Hu, Xiaowei Li, Keheng Huang, 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Hungarian algorithm based virtualization to maintain application timing similarity for defect-tolerant NoC

Xiaowei Li, Shangping Ren, Zheng Li, 2012, 17th Asia and South Pacific Design Automation Conference.

A New Multiple-Round DOR Routing for 2D Network-on-Chip Meshes

Huawei Li, Xiaowei Li, Yinhe Han, 2009, 2009 15th IEEE Pacific Rim International Symposium on Dependable Computing.

DCPUF: Placement and Routing Constraint based Dynamically Configured Physical Unclonable Function on FPGA (Abstact Only)

Yu Hu, Xiaowei Li, Jing Ye, 2016, FPGA.

DISCO: A low overhead in-network data compressor for energy-efficient chip multi-processors

Jun Zhou, Huawei Li, Xiaowei Li, 2016, 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC).

Online timing variation tolerance for digital integrated circuits

Xiaowei Li, Guihai Yan, 2011, 2011 IEEE International Test Conference.

Substantial Fault Pair At-a-Time (SFPAT): An Automatic Diagnostic Pattern Generation Method

Yu Hu, Xiaowei Li, Jing Ye, 2010, 2010 19th IEEE Asian Test Symposium.

An expression's single fault model and the testing methods

Yunzhan Gong, Xiaowei Li, Wanli Xu, 2003, 2003 Test Symposium.

The monotonic increasing relationship between average powers of CMOS VLSI circuits with and without delay and its applications

Xiaowei Li, Zuying Luo, Shiyuan Yang, 2007, Science in China Series F: Information Sciences.

Design error diagnosis based on verification techniques [logic IC design]

Xiaowei Li, Ming Shao, Guanghui Li, 2003, 2003 Test Symposium.

An energy-efficient link quality monitoring scheme for wireless networks

Xiaowei Li, Hongsong Zhu, Yongjun Xu, 2012, Wirel. Commun. Mob. Comput..

Statistical lifetime reliability optimization considering joint effect of process variation and aging

Huawei Li, Xiaowei Li, Song Jin, 2011, Integr..

Deterministic Diagnostic Pattern Generation (DDPG) for Compound Defects

Yu Huang, Fei Wang, Huawei Li, 2008, 2008 IEEE International Test Conference.

Storage assignment policy with awareness of energy consumption in the Kiva mobile fulfilment system

Xiaowei Li, Guowei Hua, Jiuh-Biing Sheu, 2020 .

IVF: Characterizing the vulnerability of microprocessor structures to intermittent faults

Yu Hu, Xiaowei Li, Songjun Pan, 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

The design-for-testability features of a general purpose microprocessor

Yu Hu, Hui Liu, Huawei Li, 2007, 2007 IEEE International Test Conference.

Processor design considerations for wireless sensor network

Tao Lv, Xiaowei Li, Yongjun Xu, 2005, 2005 6th International Conference on ASIC.

A Routing Algorithm for Random Error Tolerance in Network-on-Chip

Huawei Li, Xiaowei Li, Lei Zhang, 2007, HCI.

A Lightweight Scheme for Trust Relationship Establishment in Ubiquitous Sensor Networks

Lei Xie, Xiaowei Li, Yuefei Zhu, 2006, The Sixth IEEE International Conference on Computer and Information Technology (CIT'06).

A Scan Chain Adjustment Technology for Test Power Reduction

Xiaowei Li, Jia Li, Yu Hu, 2006, 2006 15th Asian Test Symposium.

Embedded test resource for SoC to reduce required tester channels based on advanced convolutional codes

Huawei Li, Xiaowei Li, Yinhe Han, 2006, IEEE Transactions on Instrumentation and Measurement.

Huawei Li, Xiaowei Li, Yun Cheng, 2015, 2015 IEEE Computer Society Annual Symposium on VLSI.

Scan Data Volume Reduction Using Periodically Alterable MUXs Decompressor

Yu Hu, Xiaowei Li, Yinhe Han, 2005, 14th Asian Test Symposium (ATS'05).

Statistical SDFC: A metric for evaluating test quality of small delay faults

Huawei Li, Xiaowei Li, Xuefeng Zhu, 2012, Proceedings of Technical Program of 2012 VLSI Design, Automation and Test.

Variation-Aware Scheduling for Chip Multiprocessors with Thread Level Redundancy

Xiaowei Li, Yinhe Han, Lei Zhang, 2009, 2009 15th IEEE Pacific Rim International Symposium on Dependable Computing.

Observability Statement Coverage Based on Dynamic Factored Use-Definition Chains for Functional Verification

Xiaowei Li, Tao Lv, Jianping Fan, 2006, J. Electron. Test..

TSV Minimization for Circuit — Partitioned 3D SoC Test Wrapper Design

Lei Zhang, Xiaowei Li, Yinhe Han, 2013, Journal of Computer Science and Technology.

A design- for-diagnosis technique for diagnosing both scan chain faults and combinational circuit faults

Yu Hu, Fei Wang, Huawei Li, 2008, 2008 Asia and South Pacific Design Automation Conference.

OPUF: Obfuscation logic based physical unclonable function

Yu Hu, Xiaowei Li, Jing Ye, 2015, 2015 IEEE 21st International On-Line Testing Symposium (IOLTS).

RADAR: a case for retention-aware DRAM assembly and repair in future FGR DRAM memory

Cheng Wang, Huawei Li, Xiaowei Li, 2015, DAC.

SuperRange: Wide operational range power delivery design for both STV and NTV computing

Xin He, Xiaowei Li, Yinhe Han, 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Power property analysis for CMOS integrated circuits

Xiaowei Li, Yongjun Xu, Chaonong Xu, 2005, 2005 6th International Conference on ASIC.

Improving complex distributed software system availability through information hiding

Xiaowei Li, Kevin A. Kwiat, Shangping Ren, 2010, SAC '10.

ShuttleNoC: Boosting on-chip communication efficiency by enabling localized power adaptation

Xiaowei Li, Yinhe Han, Ying Wang, 2015, The 20th Asia and South Pacific Design Automation Conference.

Simulate-the-hardware: training accurate binarized neural networks for low-precision neural accelerators

Ying Wang, Jiajun Li, Xiaowei Li, 2019, ASP-DAC.

HHC: Hierarchical hardware checkpointing to accelerate fault recovery for SRAM-based FPGAs

Yu Hu, Xiaowei Li, Hongjin Liu, 2013, 2013 IEEE 19th International On-Line Testing Symposium (IOLTS).

FT-SPEED: A Fault-Tolerant, Real-Time Routing Protocol for Wireless Sensor Networks

Xiaowei Li, Lei Zhao, Yongjun Xu, 2007, 2007 International Conference on Wireless Communications, Networking and Mobile Computing.

Lifetime Enhancement Techniques for PCM-Based Image Buffer in Multimedia Applications

Huawei Li, Xiaowei Li, Yuntan Fang, 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

On generation of a universal path candidate set containing testable long paths

Huawei Li, Xiaowei Li, Zijian He, 2010, 2010 IEEE International Test Conference.

Exploiting deterministic TPG for path delay testing

Xiaowei Li, Paul Y. S. Cheung, 2008, Journal of Computer Science and Technology.

Selection of Crosstalk-Induced Faults in Enhanced Delay Test

Huawei Li, Xiaowei Li, Huawei Li, 2005, J. Electron. Test..

Automatic Test Program Generation Using Executing-Trace-Based Constraint Extraction for Embedded Processors

Ying Zhang, Huawei Li, Xiaowei Li, 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Compression/scan co-design for reducing test data volume, scan-in power dissipation and test application time

Yu Hu, Huawei Li, Xiaowei Li, 2005, 11th Pacific Rim International Symposium on Dependable Computing (PRDC'05).

Compression/Scan Co-design for Reducing Test Data Volume, Scan-in Power Dissipation, and Test Application Time

Yu Hu, Huawei Li, Xiaowei Li, 2006, IEICE Trans. Inf. Syst..

Conference Reports

Xiaowei Li, 2004, IEEE Design & Test of Computers.

Path constraint solving based test generation for observability-enhanced branch coverage

Huawei Li, Xiaowei Li, Yanhong Zhou, 2016, 2016 IEEE 34th VLSI Test Symposium (VTS).

Vector extraction for average total power estimation

Xiaowei Li, Zuying Luo, Yongjun Xu, 2005, ASP-DAC.

ACR: Enabling computation reuse for approximate computing

Xin He, Xiaowei Li, Yinhe Han, 2016, 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC).

LFSR-Based Deterministic TPG for Two-Pattern Testing

Xiaowei Li, Hideo Fujiwara, Paul Y. S. Cheung, 2000, J. Electron. Test..

An on-chip frequency programmable test clock generation and application method for small delay defect detection

Songwei Pei, Huawei Li, Xiaowei Li, 2015, Integr..

Directed Flooding with Self-Pruning in Wireless Sensor Networks

Xiaowei Li, Yongjun Xu, Jianliang Gao, 2007, 2007 IEEE International Conference on Integration Technology.

An accurate algorithm for computing mutation coverage in model checking

Huawei Li, Xiaowei Li, Bo Liu, 2016, 2016 IEEE International Test Conference (ITC).

TURO: A lightweight turn-guided routing scheme for 3D NoCs

Jun Zhou, Huawei Li, Xiaowei Li, 2015, 2015 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS XVIII).

A maximum total leakage current estimation method

Xiaowei Li, Zuying Luo, Yongjun Xu, 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

Functional test generation guided by steady-state probabilities of abstract design

Jian Wang, Huawei Li, Xiaowei Li, 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Data Mining via Minimal Spanning Tree Clustering for Prolonging Lifetime of Wireless Sensor Networks

Jing He, Guangyan Huang, Xin Li, 2007, Int. J. Inf. Technol. Decis. Mak..

A Sensor Network Performance Inference Algorithm Based on Passive Measurement

Xiaowei Li, Yu Yang, Yongjun Xu, 2009, 2009 IEEE Wireless Communications and Networking Conference.

An On-Line Timing Error Detection Method for Silicon Debug

Huawei Li, Xiaowei Li, Yun Cheng, 2014, 2014 IEEE 23rd Asian Test Symposium.

Robust test generation for power supply noise induced path delay faults

Yu Hu, Huawei Li, Xiaowei Li, 2008, 2008 Asia and South Pacific Design Automation Conference.

IVF: characterizing the vulnerability of microprocessor structures to intermittent faults

Yu Hu, Xiaowei Li, Songjun Pan, 2010, DATE 2010.

Clustering Versus Evenly Distributing Energy Dissipation in Wireless Sensor Routing for Prolonging Network Lifetime

Jing He, Guangyan Huang, Xiaowei Li, 2006, International Conference on Computational Science.

Thermal-Constrained Task Allocation for Interconnect Energy Reduction in 3-D Homogeneous MPSoCs

Xiaowei Li, Yinhe Han, Lei Zhang, 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Partial-SET: Write speedup of PCM main memory

Yu Hu, Xiaowei Li, Bing Li, 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Observation Point Oriented Deterministic Diagnosis Pattern Generation (DDPG) for Chain Diagnosis

Yu Hu, Fei Wang, Xiaowei Li, 2008, 2008 17th Asian Test Symposium.

ZoneDefense: A Fault-Tolerant Routing for 2-D Meshes Without Virtual Channels

Huawei Li, Xiaowei Li, Yinhe Han, 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Design of an efficient memory subsystem for network processor

Tong Liu, Huawei Li, Xiaowei Li, 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

On Topology Reconfiguration for Defect-Tolerant NoC-Based Homogeneous Manycore Systems

Qiang Xu, Huawei Li, Xiaowei Li, 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Energy-efficiency analysis of cluster-based routing protocols in wireless sensor networks

Guangyan Huang, Xiaowei Li, Jing He, 2006, 2006 IEEE Aerospace Conference.

Vertical interconnects squeezing in symmetric 3D mesh Network-on-Chip

Xiaowei Li, Cheng Liu, Yinhe Han, 2011, 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011).

Performance-asymmetry-aware scheduling for Chip Multiprocessors with static core coupling

Xiaowei Li, Yinhe Han, Lei Zhang, 2010, J. Syst. Archit..

AgileRegulator: A hybrid voltage regulator scheme redeeming dark silicon for power efficiency in a multicore architecture

Minyi Guo, Xiaowei Li, Yinhe Han, 2012, IEEE International Symposium on High-Performance Comp Architecture.

Test power optimization techniques for CMOS circuits

Huawei Li, Xiaowei Li, Zuying Luo, 2002, Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02)..

Low power processor design for wireless sensor network applications

Tao Lv, Xiaowei Li, Yongjun Xu, 2005, Proceedings. 2005 International Conference on Wireless Communications, Networking and Mobile Computing, 2005..

Embedded Test Decompressor to Reduce the Required Channels and Vector Memory of Tester for Complex Processor Circuit

Yu Hu, Huawei Li, Xiaowei Li, 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A cost-effective substantial-impact-filter based method to tolerate voltage emergencies

Yu Hu, Xiaowei Li, Xing Hu, 2011, 2011 Design, Automation & Test in Europe.

Off-path leakage power aware routing for SRAM-based FPGAs

Yu Hu, Xiaowei Li, Hongjin Liu, 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).

NXG05-4: Fast Packet Classification using Group Bit Vector

Tong Liu, Huawei Li, Xiaowei Li, 2006, IEEE Globecom 2006.

Extended Selective Encoding of Scan Slices for Reducing Test Data and Test Power

Xiaowei Li, Jun Liu, Yinhe Han, 2010 .

Fast path selection for testing of small delay defects considering path correlations

Huawei Li, Xiaowei Li, Zijian He, 2010, 2010 28th VLSI Test Symposium (VTS).

Orchestrator: Guarding Against Voltage Emergencies in Multithreaded Applications

Yu Hu, Xiaowei Li, Xing Hu, 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A Self-Repairable Microprocessor

Yu Hu, Xiaowei Li, Yang Zhao, 2009 .

The Automatic Generation of Basis Set of Path for Path Testing

Xiaowei Li, Chen Rui, Han Congying, 2005, 14th Asian Test Symposium (ATS'05).

EcoUp: Towards Economical Datacenter Upgrading

Xiaowei Li, Jun Ma, Yinhe Han, 2016, IEEE Transactions on Parallel and Distributed Systems.

Using MUXs network to hide bunches of scan chains

Yu Hu, Huawei Li, Xiaowei Li, 2005, Sixth international symposium on quality electronic design (isqed'05).

Leveraging the core-level complementary effects of PVT variations to reduce timing emergencies in multi-core processors

Xiaowei Li, Yinhe Han, Xiaoyao Liang, 2010, ISCA '10.

Theoretic analysis and enhanced X-tolerance of test response compact based on convolutional code

Yu Hu, Huawei Li, Xiaowei Li, 2005, ASP-DAC.

A Thermal-Aware Parallel Multicast Testing Method Based on Many-Core Chips: A Thermal-Aware Parallel Multicast Testing Method Based on Many-Core Chips

Xiaowei Li, Fang Fang, Yinhe Han, 2010 .

Testable Path Selection and Grouping for Faster Than At-Speed Testing

Huawei Li, Xiaowei Li, Xiang Fu, 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Extended Selective Encoding of Scan Slices for Reducing Test Data and Test Power

Xiaowei Li, Jun Liu, Yinhe Han, 2009, 2009 Asian Test Symposium.

Addressing the issue of processing element under-utilization in general-purpose systolic deep learning accelerators

Ying Wang, Jiajun Li, Xiaoming Chen, 2019, ASP-DAC.

Leakage current estimation of CMOS circuit with stack effect

Xiaowei Li, Zuying Luo, Xianlong Hong, 2008, Journal of Computer Science and Technology.

Impact assessment of net metering on smart home cyberattack detection

Jie Wu, Yang Liu, Yu Hu, 2015, 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC).

Test Resource Partitioning Based on Efficient Response Compaction for Test Time and Tester Channels Reduction

Huawei Li, Xiaowei Li, Yinhe Han, 2005, Journal of Computer Science and Technology.

AnOn-chip Combinational Decompressor forReducing TestDataVolume

Xiaowei Li, Yinhe Han, Xiaowei Li, 2006 .

M-IVC: Using Multiple Input Vectors to Minimize Aging-Induced Delay

Huawei Li, Xiaowei Li, Song Jin, 2009, 2009 Asian Test Symposium.

Enhanced Wear-Rate Leveling for PRAM Lifetime Improvement Considering Process Variation

Xiaowei Li, Yinhe Han, Ying Wang, 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

MicroFix: Using timing interpolation and delay sensors for power reduction

Hui Liu, Xiaowei Li, Yinhe Han, 2011, TODE.

A novel abstraction-guided simulation approach using posterior probabilities for verification

Jian Wang, Huawei Li, Xiaowei Li, 2014, Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test.

On reducing both shift and capture power for scan-based testing

Yu Hu, Qiang Xu, Xiaowei Li, 2008, 2008 Asia and South Pacific Design Automation Conference.

RevivePath: Resilient Network-on-Chip Design Through Data Path Salvaging of Router

Lei Zhang, Xiaowei Li, Cheng Liu, 2013, Journal of Computer Science and Technology.

Channel Width Utilization Improvement in Testing NoC-Based Systems for Test Time Reduction

Yu Hu, Qiang Xu, Xiaowei Li, 2008, 4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008).

Unified Capture Scheme for Small Delay Defect Detection and Aging Prediction

Huawei Li, Xiaowei Li, Song Jin, 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Passive Loss Inference in Wireless Sensor Networks Using EM Algorithm

Xiaowei Li, Yu Yang, Yongjun Xu, 2010, Wirel. Sens. Netw..

Impact of Hazards on Pattern Selection for Small Delay Defects

Jie Wang, Huawei Li, Xiaowei Li, 2009, 2009 15th IEEE Pacific Rim International Symposium on Dependable Computing.

CuckooPIM: an efficient and less-blocking coherence mechanism for processing-in-memory systems

Ying Wang, Xiaoming Chen, Xiaowei Li, 2019, ASP-DAC.

Data-aware DRAM refresh to squeeze the margin of retention time in hybrid memory cube

Huawei Li, Xiaowei Li, Yinhe Han, 2014, 2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

A signal degradation reduction method for memristor ratioed logic (MRL) gates

Xiaowei Li, Yinhe Han, Ying Wang, 2015, IEICE Electron. Express.

Circuit-width based heuristic for Boolean reasoning

Xiaowei Li, Guanghui Li, 2004, 13th Asian Test Symposium.

Flip-Flop Selection for Transition Test Pattern Reduction Using Partial Enhanced Scan

Songwei Pei, Huawei Li, Xiaowei Li, 2009, 2009 15th IEEE Pacific Rim International Symposium on Dependable Computing.

Online distributed fault detection of sensor measurements

Xiaowei Li, Yongjun Xu, Jianliang Gao, 2007 .

Embedded Test Resource to Reduce the Required Memory and Channels of Tester

Huawei Li, Xiaowei Li, Yinhe Han, 2005, 2005 IEEE Instrumentationand Measurement Technology Conference Proceedings.

On Selection of Testable Paths with Specified Lengths for Faster-Than-At-Speed Testing

Huawei Li, Xiaowei Li, Xiang Fu, 2010, 2010 19th IEEE Asian Test Symposium.

An abacus turn model for time/space-efficient reconfigurable routing

Huawei Li, Xiaowei Li, Jun Ma, 2011, 2011 38th Annual International Symposium on Computer Architecture (ISCA).

LEGR: A Load-Balanced and Energy-Efficient Geographic Routing for Lossy Wireless Sensor Network

Xiaowei Li, Lei Zhao, Hongsong Zhu, 2007, 2007 3rd International Conference on Intelligent Sensors, Sensor Networks and Information.

Strong self-testability for data paths high-level synthesis

Xiaowei Li, Toshimitsu Masuzawa, Hideo Fujiwara, 2000, Proceedings of the Ninth Asian Test Symposium.

BoDNoC: Providing bandwidth-on-demand interconnection for multi-granularity memory systems

Xiaowei Li, Yinhe Han, Ying Wang, 2017, 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC).

Linear Pulse-Coupled Oscillators Model¬ - A New Approach for Time Synchronization in Wireless Sensor Networks

Xiaowei Li, Hongsong Zhu, Yongjun Xu, 2010, Wirel. Sens. Netw..

Diagnosis and Layout Aware (DLA) scan chain stitching

Yu Hu, Xiaowei Li, Jing Ye, 2013, 2013 IEEE International Test Conference (ITC).

POSTER: Attack on Non-Linear Physical Unclonable Function

Yu Hu, Xiaowei Li, Jing Ye, 2016, CCS.

DeepBurning: Automatic generation of FPGA-based learning accelerators for the Neural Network family

Jie Xu, Huawei Li, Xiaowei Li, 2016, 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC).

Dynamic Minimal Spanning Tree Routing Protocol for Large Wireless Sensor Networks

Guangyan Huang, Xiaowei Li, Jing He, 2006, 2006 1ST IEEE Conference on Industrial Electronics and Applications.

Retraining-based timing error mitigation for hardware neural networks

Huawei Li, Xiaowei Li, David Novo, 2015, 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE).

ReviveNet: A Self-Adaptive Architecture for Improving Lifetime Reliability via Localized Timing Adaptation

Xiaowei Li, Yinhe Han, Guihai Yan, 2011, IEEE Transactions on Computers.

Amphisbaena: Modeling two orthogonal ways to hunt on heterogeneous many-cores

Xiaowei Li, Jun Ma, Yinhe Han, 2014, 2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC).