J R Ahlbin

SEU Prediction From SET Modeling Using Multi-Node Collection in Bulk Transistors and SRAMs Down to the 65 nm Technology Node

R A Reed, R A Weller, R D Schrimpf, 2011, IEEE Transactions on Nuclear Science.

Independent Measurement of SET Pulse Widths From N-Hits and P-Hits in 65-nm CMOS

B L Bhuva, L W Massengill, B Narasimham, 2010, IEEE Transactions on Nuclear Science.

Single-Event Transient Measurements in nMOS and pMOS Transistors in a 65-nm Bulk CMOS Technology at Elevated Temperatures

B L Bhuva, R D Schrimpf, B Narasimham, 2011, IEEE Transactions on Device and Materials Reliability.

Alpha-Particle and Focused-Ion-Beam-Induced Single-Event Transient Measurements in a Bulk 65-nm CMOS Technology

B L Bhuva, R A Reed, R D Schrimpf, 2011, IEEE Transactions on Nuclear Science.

The Effect of Layout Topology on Single-Event Transient Pulse Quenching in a 65 nm Bulk CMOS Process

B L Bhuva, R A Reed, J R Ahlbin, 2010, IEEE Transactions on Nuclear Science.

Layout Technique for Single-Event Transient Mitigation via Pulse Quenching

W. T. Holman, B L Bhuva, W T Holman, 2011, IEEE Transactions on Nuclear Science.