Raymond R. Hoare

发表

A hybrid encoding scheme for efficient single-cycle range matching in content addressable memory

Alex K. Jones, Ying Yu, Raymond R. Hoare, 2006, 2006 IEEE International Symposium on Circuits and Systems.

An 88-way multiprocessor within an FPGA with customizable instructions

Shen Chih Tung, Raymond R. Hoare, Katrina Werger, 2004, 18th International Parallel and Distributed Processing Symposium, 2004. Proceedings..

A framework for the design, synthesis and cycle-accurate simulation of multiprocessor networks

Rami G. Melhem, Alex K. Jones, Shen Chih Tung, 2005, J. Parallel Distributed Comput..

Reducing power while increasing performance with supercisc

Alex K. Jones, John Foster, Gayatri Mehta, 2006, TECS.

Design Automation for RFID Tags and Systems

Marlin H. Mickle, Alex K. Jones, James T. Cain, 2008 .

A CAM-based intrusion detection system for single-packet attack detection

Alex K. Jones, Ying Yu, Raymond R. Hoare, 2008, 2008 IEEE International Symposium on Parallel and Distributed Processing.

A Field Programmable RFID Tag and Associated Design Flow

Marlin H. Mickle, Alex K. Jones, Swapna R. Dontharaju, 2006, 2006 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines.

Object-oriented aggregate networks

Henry G. Dietz, Raymond R. Hoare, 1999 .

Cyclical cascade chains: a dynamic barrier synchronization mechanism for multiprocessor systems

Raymond R. Hoare, Troy A. Johnson, 2001, Proceedings 15th International Parallel and Distributed Processing Symposium. IPDPS 2001.

Switch design to enable predictive multiplexed switching in multiprocessor networks

Rami G. Melhem, Alex K. Jones, Jiang Zheng, 2005, 19th IEEE International Parallel and Distributed Processing Symposium.

An FPGA-based VLIW processor with custom hardware execution

Alex K. Jones, John Foster, Raymond R. Hoare, 2005, FPGA '05.

A Low-Energy Reconfigurable Fabric for the SuperCISC Architecture

Alex K. Jones, Gayatri Mehta, Raymond R. Hoare, 2006, 2006 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines.

Greedy Algorithms for Mapping onto a Coarse-grained Reconfigurable Fabric 1

Alex K. Jones, Oleg A. Prokopyev, Raymond R. Hoare, 2008 .

An automated, FPGA-based reconfigurable, low-power RFID tag

Marlin H. Mickle, Alex K. Jones, Swapna R. Dontharaju, 2007, Microprocess. Microsystems.

Rapid VLIW Processor Customization for Signal Processing Applications Using Combinational Hardware Functions

Alex K. Jones, John Foster, Shen Chih Tung, 2006, EURASIP J. Adv. Signal Process..

Technology Mapping for Field Programmable Gate Arrays using Content-Addressable Memory (CAM)

Alex K. Jones, Raymond R. Hoare, Ivan S. Kourtev, 2006, 2006 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines.

Aframeworkforthedesign,synthesisandcycle-accuratesimulationof multiprocessornetworks !

Alex K. Jones, Rami Melhem, Raymond R. Hoare, 2005 .

Technology Mapping for Field Programmable Gate Arrays using Content-Addressable Memory (CAM)

Alex K. Jones, Raymond R. Hoare, Ivan S. Kourtev, 2006, FCCM.

Cross‐institutional assessment: Development and implementation of the On‐line Student Survey System

Mary Besterfield-Sacre, Larry J. Shuman, Raymond R. Hoare, 2002, Comput. Appl. Eng. Educ..

Design space exploration for low-power reconfigurable fabrics

Alex K. Jones, Gayatri Mehta, Raymond R. Hoare, 2006, Proceedings 20th IEEE International Parallel & Distributed Processing Symposium.

Adaptive hybrid switching technique for parallel computing system

Raymond R. Hoare, Zhu Ding, R. Hoare, 2006 .

Accelerating SAR processing on COTS FPGA hardware using C-to-gates design tools

Raymond R. Hoare, Denis Smetana, R. Hoare, 2014, 2014 IEEE High Performance Extreme Computing Conference (HPEC).

Speech silicon AM: an FPGA-based acoustic modeling pipeline for hidden Markov model based speech recognition

Raymond R. Hoare, Kshitij Gupta, Jeffrey William Schuster, 2006, Proceedings 20th IEEE International Parallel & Distributed Processing Symposium.

Linking Compilation and Visualization for Massively Parallel Programs

Rami G. Melhem, Shuyi Shao, Alex K. Jones, 2007, 2007 IEEE International Parallel and Distributed Processing Symposium.

VLIW across multiple superscalar processors on a single chip

Henry G. Dietz, Raymond R. Hoare, Soohong P. Kim, 1997, Proceedings 1997 International Conference on Parallel Architectures and Compilation Techniques.

A 64-way VLIW/SIMD FPGA architecture and design flow

Alex K. Jones, John Foster, Raymond R. Hoare, 2004, Proceedings of the 2004 11th IEEE International Conference on Electronics, Circuits and Systems, 2004. ICECS 2004..

Interconnect routing and scheduling - Level-wise scheduling algorithm for fat tree interconnection networks

Rami G. Melhem, Alex K. Jones, Raymond R. Hoare, 2006, SC.

Extracting speedup from C-code with poor instruction-level parallelism

Alex K. Jones, John Foster, Raymond R. Hoare, 2005, 19th IEEE International Parallel and Distributed Processing Symposium.

Passive active radio frequency identification tags

Marlin H. Mickle, Alex K. Jones, Peter J. Hawrylak, 2006, Int. J. Radio Freq. Identif. Technol. Appl..

An automated, reconfigurable, low-power RFID tag

Marlin H. Mickle, Alex K. Jones, Swapna R. Dontharaju, 2006, 2006 43rd ACM/IEEE Design Automation Conference.

Short Courses in System-on-a-Chip (SoC) design

Donald M. Chiarulli, Steven P. Levitan, Bruce R. Childers, 2003, Proceedings 2003 IEEE International Conference on Microelectronic Systems Education. MSE'03.

A case for aggregate networks

Henry G. Dietz, Raymond R. Hoare, 1998, Proceedings of the First Merged International Parallel Processing Symposium and Symposium on Parallel and Distributed Processing.

Bitwise aggregate networks

Henry G. Dietz, Raymond R. Hoare, Timothy Mattox, 1996, Proceedings of SPDP '96: 8th IEEE Symposium on Parallel and Distributed Processing.

Interconnect routing and scheduling - A near-optimal real-time hardware scheduler for large cardinality crossbar switches

Alex K. Jones, Raymond R. Hoare, Zhu Ding, 2006, SC.

A fine-grain parallel architecture based on barrier synchronization

Henry G. Dietz, Raymond R. Hoare, Timothy Mattox, 1996, Proceedings of the 1996 ICPP Workshop on Challenges for Parallel Processing.

A VLIW Processor With Hardware Functions: Increasing Performance While Reducing Power

Alex K. Jones, Gayatri Mehta, Raymond R. Hoare, 2006, IEEE Transactions on Circuits and Systems II: Express Briefs.

A two-stage hardware scheduler combining greedy and optimal scheduling

Alex K. Jones, Raymond R. Hoare, Zhu Ding, 2008, J. Parallel Distributed Comput..

ClusterNet: An Object-Oriented Cluster Network

Raymond R. Hoare, 2000, IPDPS Workshops.

On the Feasibility of Optical Circuit Switching for High Performance Computing Systems

Rami G. Melhem, Shuyi Shao, Alex K. Jones, 2005, ACM/IEEE SC 2005 Conference (SC'05).

Combining mentor graphics' HDL designer FPGA flow with a reconfigurable system on a programmable chip, educational opportunity or insanity?

Shen Chih Tung, Raymond R. Hoare, 2003, Proceedings 2003 IEEE International Conference on Microelectronic Systems Education. MSE'03.

A Low-Energy Reconfigurable Fabric for the SuperCISC Architecture

Alex K. Jones, Gayatri Mehta, Raymond R. Hoare, 2006, J. Low Power Electron..

Optimizing technology mapping for FPGAs using CAMs

Alex K. Jones, Raymond R. Hoare, Joshua M. Lucas, 2005, 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05).

A Width Expansion of MMX/SIMD Processing Architecture on an FPGA

Raymond R. Hoare, S. Bailey, D. Swope, 2002, IASTED PDCS.

An SoC solution for massive parallel processing

David Reed, Raymond R. Hoare, 2002, Proceedings 16th International Parallel and Distributed Processing Symposium.

LURU: global-scope FPGA technology mapping with content-addressable memories

Alex K. Jones, Raymond R. Hoare, Ivan S. Kourtev, 2004, Proceedings of the 2004 11th IEEE International Conference on Electronics, Circuits and Systems, 2004. ICECS 2004..

A Gigabit Embedded Protocol Analyzer Pre-Processor

Raymond R. Hoare, Ying Yu, Jacob J. Repanshek, 2005 .

Deep Delay Loop Reservoir Computing for Specific Emitter Identification pdf

Raymond R. Hoare, Paul Toliver, William Johnson, 2020, ArXiv.

Speech Silicon: An FPGA Architecture for Real-Time Hidden Markov-Model-Based Speech Recognition

Alex K. Jones, Raymond R. Hoare, Kshitij Gupta, 2006, EURASIP J. Embed. Syst..

Radio frequency identification prototyping

Marlin H. Mickle, Alex K. Jones, Peter J. Hawrylak, 2008, TODE.