Qi Xiang

发表

Gate line-edge roughness effects in 50-nm bulk MOSFET devices

Shiying Xiong, Jeffrey Bokor, Qi Xiang, 2002, SPIE Advanced Lithography.

Hot-carrier effects in sub-100-nm gate-length N-MOSFETs with thermal and nitrided oxide thickness down to 1.3 nm

Qi Xiang, Miryeong Song, Geoffrey Choh-Fei Yeap, 1998, Advanced Lithography.

Bin Yu, Haihong Wang, Qi Xiang, 2002, Digest. International Electron Devices Meeting,.

Advanced compact modeling of logic devices toward CMOS scaling limits

Qiang Chen, Qi Xiang, J.X. An, 2004, Proceedings. 7th International Conference on Solid-State and Integrated Circuits Technology, 2004..

High-k scaling for gate insulators: an insightful study

Bin Yu, Qi Xiang, Ming-Ren Lin, 1998, Advanced Lithography.

Multiple Gate MOSFETs

Zoran Krivokapic, Qi Xiang, Ming-Ren Lin, 2006 .

Process-design co-optimization for FPGA

Qi Xiang, 2008, 2008 9th International Conference on Solid-State and Integrated-Circuit Technology.

An Exploration of Energy Loss in Connecting Two Capacitors

Qi Xiang, 2009 .

Advanced technology for FPGAs

Qi Xiang, 2010, 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology.

Dielectrics in SI nano-devices: Roles and challenges

Zoran Krivokapic, Qi Xiang, Ming-Ren Lin, 2004 .

Nanoscale CMOS at low temperature: design, reliability, and scaling trend

Bin Yu, Qi Xiang, C. Riccobene, 2001, 2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517).

Sub-100-nm and deep sub-100-nm MOS transistor gate patterning

Christopher A. Spence, Qi Xiang, Bhanwar Singh, 1998, Advanced Lithography.

Impact of tunnel currents and channel resistance on the characterization of channel inversion layer charge and polysilicon-gate depletion of sub-20-/spl Aring/ gate oxide MOSFETs

Qi Xiang, Jimmie J. Wortman, K. Ahmed, 1999 .

Very high performance 40 nm CMOS with ultra-thin nitride/oxynitride stack gate dielectric and pre-doped dual poly-Si gate electrodes

Qi Xiang, Ming-Ren Lin, K. C. Saraswat, 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).

Deep sub-100 nm CMOS with ultra low gate sheet resistance by NiSi

Qi Xiang, Ming-Ren Lin, Eric N. Paton, 2000, 2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104).

Strained silicon NMOS with nickel-silicide metal gate

S. Ahmed, Qi Xiang, Jung-Suk Goo, 2003, 2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407).

Scaling towards 35 nm gate length CMOS

Qi Xiang, Ming-Ren Lin, Joong Jeon, 2001, 2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184).

Limits of gate-oxide scaling in nano-transistors

Qi Xiang, C. Riccobene, Ming-Ren Lin, 2000, 2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104).

High performance sub-50 nm CMOS with advanced gate stack

Qi Xiang, Ming-Ren Lin, M. Lin, 2001, 2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184).

High Performance 45nm CMOS Technology with 20nm Multi-Gate Devices

Zoran Krivokapic, Qi Xiang, Ming-Ren Lin, 2003 .

15 nm gate length planar CMOS transistor

Qi Xiang, Ming-Ren Lin, Effiong Ibok, 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).