Sumio Tanaka

A 9-ns HIT-delay 32-kbyte cache macro for high-speed RISC

Sumio Tanaka, Tetsuya Iizuka, Takayasu Sakurai, 1990 .

A 0.8- mu m BiCMOS ATM switch on an 800 Mb/s asynchronous buffered banyan network

Sumio Tanaka, Kenji Maeguchi, Hiroyuki Hara, 1991 .