K. Masu

发表

Substrate-geometry aware 2-port modeling for surface-mount passive components

K. Yamanaga, T. Sato, K. Masu, 2008, 2008 Asia-Pacific Symposium on Electromagnetic Compatibility and 19th International Zurich Symposium on Electromagnetic Compatibility.

A 6.5-mW 5-Gbps On-Chip Differential Transmission Line Interconnect with a Low-Latency Asymmetric Tx in a 180nm CMOS Technology

K. Masu, K. Okada, T. Ishii, 2006, 2006 IEEE Asian Solid-State Circuits Conference.

A process-scalable RF transceiver for short range communication in 90 nm Si CMOS

K. Masu, H. Ito, A. Shirane, 2012, 2012 IEEE Radio Frequency Integrated Circuits Symposium.

A multi-physics simulation technique for integrated MEMS

K. Masu, K. Machida, H. Toshiyoshi, 2012, 2012 International Electron Devices Meeting.

Near field communication chip using PIM for bio MEMS sensors

K. Masu, K. Okada, T. Yamada, 2004, Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits.

On-chip transmission line for long global interconnects

K. Masu, K. Okada, H. Ito, 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

An 8Gbps 2.5mW on-chip pulsed-current-mode transmission line interconnect with a stacked-switch Tx

K. Masu, H. Ito, T. Maekawa, 2008, ESSCIRC 2008 - 34th European Solid-State Circuits Conference.

Selective and nonselective deposition of aluminum by LPCVD using DMAH and microregion observation of single crystal aluminum with scanning μ-RHEED microscope

T. Matano, K. Masu, K. Tsubouchi, 1990, Digest of Technical Papers.1990 Symposium on VLSI Technology.

High speed and low power global interconnect IP with differential transmission line and driver-receiver circuits

K. Masu, K. Okada, H. Ito, 2004, Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits.

Non-invasive direct probing for on-chip voltage measurement

K. Yamanaga, T. Sato, K. Masu, 2008, 2008 International SoC Design Conference.

SMAFTI packaging technology for new interconnect hierarchy

K. Masu, S. Amakawa, M. Kawano, 2009, 2009 IEEE International Interconnect Technology Conference.

Accurate Array-Based Measurement for Subthreshold-Current of MOS Transistors

T. Sato, K. Masu, H. Ueyama, 2009, IEEE Journal of Solid-State Circuits.

A Single-Platform Simulation and Design Technique for CMOS-MEMS Based on a Circuit Simulator With Hardware Description Language

K. Masu, K. Machida, H. Toshiyoshi, 2013, Journal of Microelectromechanical Systems.

On-Chip High-$Q$Variable Inductor Using Wafer-Level Chip-Scale Package Technology

T. Ito, K. Masu, K. Okada, 2006, IEEE Transactions on Electron Devices.

Reconfigurable CMOS LNA for software defined radio using variable inductor

K. Masu, H. Sugawara, K. Okada, 2005, 2005 European Microwave Conference.

A Reconfigurable RF Circuit Architecture for Dynamic Power Reduction

K. Masu, T. Ito, K. Okada, 2005, TENCON 2005 - 2005 IEEE Region 10 Conference.

High speed and low power on-chip micro network circuit with differential transmission line

K. Masu, K. Okada, H. Ito, 2004, 2004 International Symposium on System-on-Chip, 2004. Proceedings..

One chip demodulator using RF front-end SAW correlator for 2.4 GHz asynchronous spread spectrum modem

K. Masu, H. Nakase, T. Kasai, 1994, 5th IEEE International Symposium on Personal, Indoor and Mobile Radio Communications, Wireless Networks - Catching the Mobile Future..

A 0.98 to 6.6 Hz Tunable Wideband VCO in a 180nm CMOS Technology for Reconfigurable Radio Transceiver

K. Masu, H. Sugawara, K. Okada, 2006, 2006 IEEE Asian Solid-State Circuits Conference.

On the validity of bisection-based thru-only de-embedding

K. Masu, S. Amakawa, T. Sekiguchi, 2010, 2010 International Conference on Microelectronic Test Structures (ICMTS).

A Bidirectional- and Multi-Drop-Transmission-Line Interconnect for Multipoint-to-Multipoint On-Chip Communications

K. Okada, K. Masu, T. Ishii, 2008, IEEE Journal of Solid-State Circuits.

CMOS-MEMS -new frontier of multilevel interconnect technology

K. Masu, K. Machida, H. Toshiyoshi, 2015, 2015 International Conference on Electronic Packaging and iMAPS All Asia Conference (ICEP-IAAC).

S-Parameter-Based Modal Decomposition of Multiconductor Transmission Lines and Its Application to De-Embedding

K. Masu, H. Ito, S. Amakawa, 2009, 2009 IEEE International Conference on Microelectronic Test Structures.

A 1.7-GHz 1.5-mW digitally-controlled FBAR oscillator with 0.03-ppb resolution

K. Masu, K. Soumyanath, H. Ito, 2008, ESSCIRC 2008 - 34th European Solid-State Circuits Conference.

On-chip differential and common mode voltage measurement using off-chip referenced twin probing

K. Yamanaga, K. Masu, T. Sato, 2008, 2008 12th IEEE Workshop on Signal Propagation on Interconnects.

4 Gbps On-Chip Interconnection using Differential Transmission Line

K. Masu, K. Okada, H. Ito, 2005, 2005 IEEE Asian Solid-State Circuits Conference.

Modeling of three-pPort Si CMOS on-chip symmetric inductor for various operation modes

K. Masu, K. Okada, H. Sugawara, 2007, 2007 European Microwave Conference.

A 8-Gbps Low-Latency Multi-Drop On-Chip Transmission Line Interconnect with 1.2-mW Two-Way Transceivers

K. Masu, K. Okada, H. Ito, 2007, 2007 IEEE Symposium on VLSI Circuits.

On-chip transmission line interconnect for Si CMOS LSI

K. Masu, K. Okada, H. Ito, 2006, Digest of Papers. 2006 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems.

A MOS transistor array with pico-ampere order precision for accurate characterization of leakage current variation

T. Sato, K. Masu, H. Ueyama, 2008, 2008 IEEE Asian Solid-State Circuits Conference.

A Loss Optimization Method Using WD Product for On-Chip Differential Transmission Line Design

K. Masu, K. Okada, H. Ito, 2006, 2006 IEEE Workship on Signal Propagation on Interconnects.

High-Crosstalk Robustness Transmission Line Interconnect in Si LSI using Zero-Crosstalk Structure

K. Masu, K. Okada, H. Ito, 2006, 2006 IEEE Workship on Signal Propagation on Interconnects.

Evaluation of on-chip transmission line interconnect using wire length distribution

K. Masu, H. Ito, T. Uezono, 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

Design of High-Density Interconnects for High-Speed Transmission

K. Masu, K. Okada, M. Kimura, 2007, 2007 Proceedings 57th Electronic Components and Technology Conference.

A dynamic reconfigurable RF circuit architecture

K. Masu, K. Okada, H. Sugawara, 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

Reconfigurable RF circuit design for multi-band wireless chip

K. Masu, K. Okada, H. Ito, 2004, Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits.

A 20 Gb/s 1:4 DEMUX with Near-Rail-to-Rail Logic Swing in 90 nm CMOS process

T. Suzuki, K. Masu, S. Amakawa, 2009, 2009 IEEE MTT-S International Microwave Workshop Series on Signal Integrity and High-Speed Interconnects.

Wide-range RF variable inductor on Si CMOS chip with MEMS actuator

K. Masu, K. Okada, H. Sugawara, 2004, 34th European Microwave Conference, 2004..

Battery-less wireless communication system through human body for in-vivo healthcare chip

K. Masu, K. Okada, T. Yamada, 2004, Digest of Papers. 2004 Topical Meeting onSilicon Monolithic Integrated Circuits in RF Systems, 2004..

An over-12-Gbps on-chip transmission line interconnect with a pre-emphasis technique in 90 nm CMOS

K. Masu, T. Ishii, H. Ito, 2008, 2008 IEEE-EPEP Electrical Performance of Electronic Packaging.

Differential transmission line structure for over 10 Gbps signal transmission at global interconnect in Si ULSI

K. Masu, K. Okada, H. Ito, 2004, Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits.

On-chip variable inductor using MOSFET switches

Khoa Dang Pham, K. Masu, K. Okada, 2005, 2005 European Microwave Conference.

Optimization methodology of global interconnect structure

K. Masu, K. Okada, T. Uezono, 2004, Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004..

On-chip high-Q spiral Cu inductors embedded in wafer-level chip-scale package for silicon RF application

K. Okada, K. Masu, K. Itoi, 2004, 2004 IEEE MTT-S International Microwave Symposium Digest (IEEE Cat. No.04CH37535).

Short-channel-effect free 0.18 /spl mu/m MOSFET by temperature-dimension combination scaling theory: design and experiment

K. Masu, M. Yokoyama, T. Hidaka, 1994, IEEE Electron Device Letters.

A 1.3-2.8 GHz Wide Range CMOS LC-VCO Using Variable Inductor

K. Okada, K. Masu, Y. Yoshihara, 2005, 2005 IEEE Asian Solid-State Circuits Conference.

A batteryless wireless communication circuit for measurement of gastric acid

K. Okada, K. Masu, Y. Kobayashi, 2006, 2006 IEEE Biomedical Circuits and Systems Conference.

On-chip high-Q solenoid inductors embedded in WL-CSP

K. Okada, K. Masu, K. Itoi, 2004, Proceedings of the Sixth IEEE CPMT Conference on High Density Microsystem Design and Packaging and Component Failure Analysis (HDP '04).

A wide tuning range CMOS VCO using variable inductor

K. Okada, K. Masu, Y. Yoshihara, 2004, Digest of Papers. 2004 Topical Meeting onSilicon Monolithic Integrated Circuits in RF Systems, 2004..

A Low-Latency and High-Power-Efficient On-Chip LVDS Transmission Line Interconnect for an RC Interconnect Alternative

K. Okada, K. Masu, H. Sugita, 2007, 2007 IEEE International Interconnect Technology Conferencee.

A low phase noise LC-VCO with a high-Q inductor fabricated by wafer level package technology

K. Okada, K. Masu, T. Aizawa, 2008, 2008 IEEE Radio Frequency Integrated Circuits Symposium.

A DC-7 GHz Small-Area Distributed Amplifier Using 5-port Inductors in a 180nm Si CMOS Technology

K. Okada, K. Masu, D. Kawazoe, 2006, 2006 IEEE Asian Solid-State Circuits Conference.

An inductorless injection-locked PLL with 1/2- and 1/4-integral subharmonic locking in 90 nm CMOS

K. Masu, N. Ishihara, S. Tanoi, 2012, 2012 IEEE Radio Frequency Integrated Circuits Symposium.

High-Q variable inductor using redistributed layers for Si RF circuits

K. Okada, K. Masu, K. Itoi, 2004, Digest of Papers. 2004 Topical Meeting onSilicon Monolithic Integrated Circuits in RF Systems, 2004..

A Multi-Band Quadrature Clock Generator With High-Pass-Filtered Pulse Injection Technique

K. Masu, A. Shirane, S. Yonezawa, 2013, IEEE Microwave and Wireless Components Letters.

Quality factor enhancement of on-chip inductor by using negative impedance circuit

K. Okada, K. Masu, K.D. Pham, 2006, Digest of Papers. 2006 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems.