Chung-Len Lee

发表

Oscillation ring based interconnect test scheme for SOC

Chauchin Su, Katherine Shu-Min Li, Chung-Len Lee, 2005, ASP-DAC.

Complete test set for multiple-valued logic networks

Chung-Len Lee, Jwu E. Chen, Hui Min Wang, 1994, Proceedings of 24th International Symposium on Multiple-Valued Logic (ISMVL'94).

Modeling and testing of interference faults in the nano NAND Flash memory

Xiaole Cui, Chung-Len Lee, Jin Zha, 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Multilevel Full-Chip Routing With Testability and Yield Enhancement

Yao-Wen Chang, Chauchin Su, Katherine Shu-Min Li, 2007, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Is IDDQ testing not applicable for deep submicron VLSI in year 2011?

Chauchin Su, Chih-Wen Lu, Chung-Len Lee, 2000, Proceedings of the Ninth Asian Test Symposium.

Structure-Based Specification-Constrained Test Frequency Generation for Linear Analog Circuits

Soon-Jyh Chang, Chung-Len Lee, Jwu E. Chen, 2003, J. Inf. Sci. Eng..

Synthesis of multi-variable MVL functions using hybrid mode CMOS logic

Chung-Len Lee, Yeong-Jar Chang, 1994, Proceedings of 24th International Symposium on Multiple-Valued Logic (ISMVL'94).

New DfT architectures for 3D-SICs with a wireless test port

Xiaole Cui, Yufeng Jin, Chung-Len Lee, 2013, 2013 IEEE 10th International Conference on ASIC.

A methodology for fault model development for hierarchical linear systems

Chauchin Su, Chung-Len Lee, Jwu E. Chen, 2000, Proceedings of the Ninth Asian Test Symposium.

IEEE standard 1500 compatible interconnect diagnosis for delay and crosstalk faults

Yao-Wen Chang, Chauchin Su, Katherine Shu-Min Li, 2006, Asia and South Pacific Conference on Design Automation, 2006..

A Two-Phase Fault Simulation Scheme for Sequential Circuits

Chung-Len Lee, Jwu E. Chen, Wen Ching Wu, 1998, J. Inf. Sci. Eng..

A low overhead DPA countermeasure of ECC based on randomized modular multiplication

Xiaole Cui, Chung-Len Lee, Shijie Zhang, 2014, 2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT).

A well-structured modified Booth multiplier design

Shyh-Jye Jou, Li-Rong Wang, Chung-Len Lee, 2008, 2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT).

Analysis of Application of the IDDQ Technique to the Deep Sub-Micron VLSI Testing

Chauchin Su, Chih-Wen Lu, Chung-Len Lee, 2002, J. Electron. Test..

Fault Diagnosis for Linear Analog Circuits

Chauchin Su, Chung-Len Lee, Jwu E. Chen, 2001, J. Electron. Test..

Invalid state identification for sequential circuit test generation

Chung-Len Lee, Jwu E. Chen, Hsing-Chung Liang, 1996, Proceedings of the Fifth Asian Test Symposium (ATS'96).

A unified approach to detecting crosstalk faults of interconnects in deep sub-micron VLSI

Chauchin Su, Katherine Shu-Min Li, Chung-Len Lee, 2004, 13th Asian Test Symposium.

Panel: New Research Problems in the Emerging Test Technology

Vishwani D. Agrawal, Bernard Courtois, Fumiyasu Hirose, 1995, Asian Test Symposium.

A test pattern selection method for dynamic burn-in of logic circuits based on ATPG technique

Chao Wang, Xiaole Cui, Chung-Len Lee, 2013, 2013 IEEE 10th International Conference on ASIC.

Oscillation Ring Delay Test for High Performance Microprocessors

Magdy S. Abadir, Chung-Len Lee, Jwu E. Chen, 2000, J. Electron. Test..

A Fast Locking-in and Low Jitter PLLWith a Process-Immune Locking-in Monitor

Chung-Len Lee, Chung-Yi Li, Hwai-Pwu Chou, 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Identification of robust untestable path delay faults

Chung-Len Lee, Jwu E. Chen, Wen Ching Wu, 1995, Proceedings of the Fourth Asian Test Symposium.

A snake addressing scheme for phase change memory testing

Xinnan Lin, Xiaole Cui, Xiaogang Chen, 2015, Science China Information Sciences.

An on-chip jitter measurement circuit for the PLL

Chung-Len Lee, Chin-Cheng Tsai, 2003, 2003 Test Symposium.

A low-power high-speed class-AB buffer amplifier for flat-panel-display application

Chih-Wen Lu, Chung-Len Lee, 2002, IEEE Trans. Very Large Scale Integr. Syst..

A new path delay test scheme based on path delay inertia

Chung-Len Lee, Ming Shae Wu, Chung Liang Chen, 2004, 13th Asian Test Symposium.

A Multiple-Sequence Generator Based on Inverted Nonlinear Autonomous Machines

Chung-Len Lee, Meng-Lieh Sheu, Meng-Lieh Sheu, 1996, IEEE Trans. Computers.

Multilevel Full-Chip Routing With Testability and Yield Enhancement

Yao-Wen Chang, Chauchin Su, Katherine Shu-Min Li, 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A UWB mixer with a balanced wide band active balun using crossing centertaped inductor

Bo Wang, Xiangrong Zhang, Xiaole Cui, 2013, 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013).

A Behavior-Level Fault Model for the Closed-Loop Operational Amplifier

Chauchin Su, Chung-Len Lee, Jwu E. Chen, 2000, J. Inf. Sci. Eng..

Factorization of multi-valued logic functions

Chung-Len Lee, Jwu E. Chen, Hui Min Wang, 1995, Proceedings 25th International Symposium on Multiple-Valued Logic.

A Multilayer Data Copy Scheme for Low Cost Test with Controlled Scan-In Power for Multiple Scan Chain Designs

Ji-Jan Chen, Chung-Len Lee, Jwu E. Chen, 2006, 2006 IEEE International Test Conference.

Maximization of power dissipation under random excitation for burn-in testing

Kuo-Chan Huang, Chung-Len Lee, Jwu E. Chen, 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

A compiled-code parallel pattern logic simulator with inertial delay model

Kuo-Chan Huang, Chung-Len Lee, Jwu E. Chen, 1997, Proceedings of 1997 IEEE International Symposium on Circuits and Systems. Circuits and Systems in the Information Age ISCAS '97.

A complement-based fast algorithm to generate universal test sets for multi-output functions

Chung-Len Lee, Beyin Chen, 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Adaptive Encoding Scheme for Test Volume/Time Reduction in SoC Scan Testing

Chung-Len Lee, Jwu E. Chen, Shih Ping Lin, 2005, 14th Asian Test Symposium (ATS'05).

Test pattern generation for static burn-in based on equivalent fault model

Xiaole Cui, Chung-Len Lee, Xinming Shi, 2013, 2013 IEEE International Conference of Electron Devices and Solid-state Circuits.

Crosstalk Fault Detection for Interconnection Lines Based on Path Delay Inertia Principle

Chung-Len Lee, Wen Ching Wu, Yeong-Jar Chang, 2005, 14th Asian Test Symposium (ATS'05).

MT-SIM a mixed-level transition fault simulator based on parallel patterns

Wen-Zen Shen, Chung-Len Lee, Ching Ping Wu, 1992, J. Electron. Test..

TRANS: a fast and memory-efficient path delay fault simulator

Chung-Len Lee, Jwu E. Chen, Meng Chiy Lin, 1994, Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC.

Identifying invalid states for sequential circuit test generation

Chung-Len Lee, Jwu E. Chen, Hsing-Chung Liang, 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Well-Structured Modified Booth Multiplier and Its Application to Reconfigurable MAC Design

Ming-Hsien Tu, Shyh-Jye Jou, Li-Rong Wang, 2011, IEICE Trans. Electron..

A Scan Matrix Design for Low Power Scan-Based Test

Chung-Len Lee, Jwu E. Chen, Shih Ping Lin, 2005, 14th Asian Test Symposium (ATS'05).

Self-heating burn-in pattern generation based on the genetic algorithm incorporated with a BACK-like procedure

Xiaole Cui, Chung-Len Lee, Xiaoxin Cui, 2015, IET Comput. Digit. Tech..

Enhanced error correction against multiple-bit-upset based on BCH code for SRAM

Xiaole Cui, Chung-Len Lee, Weijia Ma, 2013, 2013 IEEE 10th International Conference on ASIC.

An efficient test and diagnosis scheme for the feedback type of analog circuits with minimal added circuits

Chung-Len Lee, Jwu E. Chen, Jun-Weir Lin, 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

A novel test scheme for NAND flash memory based on built-in oscillator ring

Xiaole Cui, Si Chen, Chung-Len Lee, 2013, 2013 IEEE 10th International Conference on ASIC.

Fault diagnosis for linear analog circuits

Chauchin Su, Chung-Len Lee, Jwu E. Chen, 2000, Proceedings of the Ninth Asian Test Symposium.

Simplifying Sequential Circuit Test Generation

Chung-Len Lee, Meng-Lieh Sheu, 1994, IEEE Des. Test Comput..

Fault analysis on two-level (K+1)-valued logic circuits

Chung-Len Lee, Jwu E. Chen, Hui Min Wang, 1992, [1992] Proceedings The Twenty-Second International Symposium on Multiple-Valued Logic.

A folded current-reused CMOS power amplifier for low-voltage 3.0–5.0 GHz UWB applications

Bo Wang, Xiangrong Zhang, Xiaole Cui, 2013, 2013 IEEE 10th International Conference on ASIC.

An effective methodology for mixed scan and reset design based on test generation and structure of sequential circuits

Chung-Len Lee, Hsing-Chung Liang, 1999, Proceedings Eighth Asian Test Symposium (ATS'99).

A low power high speed Class-B buffer amplifier for flat panel display application

Chih-Wen Lu, Chung-Len Lee, 2002, Proceedings First IEEE International Workshop on Electronic Design, Test and Applications '2002.

A testing scheme for crosstalk faults based on the oscillation test signal [VLSI]

Chung-Len Lee, Jwu E. Chen, Ming Shae Wu, 2002, Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02)..

Single-fault fault collapsing analysis in sequential logic circuits

Wen-Zen Shen, Chung-Len Lee, Jwu E. Chen, 1990, Proceedings. International Test Conference 1990.

A new BIST scheme based on a summing-into-timing-signal principle with self calibration for the DAC

Chung-Len Lee, Jwu E. Chen, Guan-Xun Chen, 2004, 13th Asian Test Symposium.

A parallel pattern mixed-level fault simulator

Wen-Zen Shen, Chung-Len Lee, Ching Ping Wu, 1991, DAC '90.

Arbitrary Waveform Generator Based on Direct Digital Frequency Synthesizer

Chung-Len Lee, Weibo Hu, Xin'an Wang, 2008, 4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008).

Fault diagnosis of odd-even sorting networks

Chung-Len Lee, Jwu E. Chen, Wen Ching Wu, 1997, Proceedings Sixth Asian Test Symposium (ATS'97).

SEESIM-a fast synchronous sequential circuit fault simulator with single event equivalence

Wen-Zen Shen, Chung-Len Lee, Ching Ping Wu, 1992, Proceedings EURO-DAC '92: European Design Automation Conference.

Flip-Flop Selection for Mixed Scan and Reset Design Based on Test Generation and Structure of Sequential Circuits

Chung-Len Lee, Hsing-Chung Liang, 2000, J. Inf. Sci. Eng..

Distributed fault simulation for sequential circuits by pattern partitioning

Chung-Len Lee, Jwu E. Chen, Wen Ching Wu, 1994, Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC.

A reconfigurable MAC architecture implemented with mixed-Vt standard cell library

Ming-Hsien Tu, Shyh-Jye Jou, Li-Rong Wang, 2008, 2008 IEEE International Symposium on Circuits and Systems.

Analog metrology and stimulus selection in a noisy environment

Chauchin Su, Yue-Tsang Chen, Chung-Len Lee, 1999, Proceedings Eighth Asian Test Symposium (ATS'99).

All digital built-in delay and crosstalk measurement for on-chip buses

Chauchin Su, Yue-Tsang Chen, Chung-Len Lee, 2000, DATE '00.

Socillator test: a delay test scheme for embedded ICs in the boundary-scan environment

Chung-Len Lee, Tek Jau Tan, 2001, Proceedings 19th IEEE VLSI Test Symposium. VTS 2001.

Structural Fault Based Specification Reduction for Testing Analog Circuits

Soon-Jyh Chang, Chung-Len Lee, Jwu E. Chen, 2002, J. Electron. Test..

Algebraic division for multilevel logic synthesis of multi-valued logic circuits

Chung-Len Lee, Jwu E. Chen, Hui Min Wang, 1994, Proceedings of 24th International Symposium on Multiple-Valued Logic (ISMVL'94).

Impulse Radio Demodulation Scheme for Impulse Radio UWB Receiver

Xiaole Cui, Chung-Len Lee, Weibo Hu, 2014 .

Fanout fault analysis for digital logic circuits

Wen-Zen Shen, Chung-Len Lee, Jwu E. Chen, 1995, Proceedings of the Fourth Asian Test Symposium.

A computer aided engineering system for memory BIST

Chauchin Su, Chung-Len Lee, Shih-Ching Hsiao, 2001, ASP-DAC '01.

IEEE Standard 1500 Compatible Oscillation Ring Test Methodology for Interconnect Delay and Crosstalk Detection

Chauchin Su, Katherine Shu-Min Li, Chung-Len Lee, 2007, J. Electron. Test..

A Unified Detection Scheme for Crosstalk Effects in Interconnection Bus

Chauchin Su, Katherine Shu-Min Li, Chung-Len Lee, 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A Fast Two-Stage Sample-and-Hold Amplifier for Pipelined ADC Application

Jian Ruan, Chung-Len Lee, 2008, 4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008).

A programmable multiple-sequence generator for BIST applications

Chung-Len Lee, Meng-Lieh Sheu, 1995, Proceedings of the Fourth Asian Test Symposium.

A probabilitistic testability measure for delay faults

Chung-Len Lee, Wen Ching Wu, 1991, 28th ACM/IEEE Design Automation Conference.

Functional test pattern generation for CMOS operational amplifier

Soon-Jyh Chang, Chung-Len Lee, Jwu E. Chen, 1997, Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125).

All digital built-in delay and crosstalk measurement for on-chip buses

Chauchin Su, Chung-Len Lee, Mu-Jeng Huang, 2000, Proceedings Design, Automation and Test in Europe Conference and Exhibition 2000 (Cat. No. PR00537).