Mike Hutton

发表

Mike Hutton, 2015, 2015 IEEE Hot Chips 27 Symposium (HCS).

Generation of synthetic sequential benchmark circuits

Jonathan Rose, Mike Hutton, Derek G. Corneil, 1997, FPGA '97.

An FPGA Based Memory Efficient Shared Buffer Implementation

Sakir Sezer, Mike Hutton, Ciaran Toal, 2007, 2007 International Conference on Field Programmable Logic and Applications.

Arria™ 10 device architecture

Martin Langhammer, Dan Oh, David M. Lewis, 2015, 2015 IEEE Custom Integrated Circuits Conference (CICC).

Efficient static timing analysis and applications using edge masks

Mike Hutton, David Karchmer, Bryan Archell, 2005, FPGA '05.

Applications of clone circuits to issues in physical-design

Jonathan Rose, Mike Hutton, Jonathan Rose, 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).

Equivalence classes of clone circuits for physical-design benchmarking

Jonathan Rose, Mike Hutton, 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).

Integrating FPGAs in high-performance computing: introduction

Paul Chow, Mike Hutton, 2007, FPGA '07.

Interconnect enhancements for a high-speed PLD architecture

Jim Park, Mike Hutton, Rakesh H. Patel, 2002, FPGA '02.

FPGA Architecture Design Methodology

Mike Hutton, 2006, 2006 International Conference on Field Programmable Logic and Applications.

Advances and trends in FPGA design

Mike Hutton, 2004, Proceedings. SBCCI 2004. 17th Symposium on Integrated Circuits and Systems Design (IEEE Cat. No.04TH8784).

Characterization and parameterized random generation of digital circuits

Jonathan Rose, Mike Hutton, Derek G. Corneil, 1996, DAC '96.

Session details: Will power kill FPGAs?

Vaughn Betz, Mike Hutton, Jan Rabaey, 2006, FPGA '06.

MAX II: A low-cost, high-performance LUT-based CPLD

David M. Lewis, Mike Hutton, Brad Vest, 2004, Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571).

Session details: Poster session 3: applications and implementations

Mike Hutton, 2008, FPGA '08.

Automatic generation of synthetic sequential benchmark circuits

Jonathan Rose, Mike Hutton, Derek G. Corneil, 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Timing constraint-driven technology mapping for FPGAs considering false paths and multi-clock domains

Martin D. F. Wong, Deming Chen, Mike Hutton, 2007, 2007 IEEE/ACM International Conference on Computer-Aided Design.

Significant papers from the first 25 years of the FPL conference

Marco Platzner, Viktor K. Prasanna, Hideharu Amano, 2015, 2015 25th International Conference on Field Programmable Logic and Applications (FPL).

Architecture and CAD for FPGAs

Mike Hutton, 2004, Proceedings. SBCCI 2004. 17th Symposium on Integrated Circuits and Systems Design (IEEE Cat. No.04TH8784).

Improving FPGA Performance and Area Using an Adaptive Logic Module

Sinan Kaptanoglu, David M. Lewis, Mike Hutton, 2004, FPL.

Statistical placement for FPGAs considering

Yan Lin, Lei He, Mike Hutton, 2007, IET Comput. Digit. Tech..

INVITED PAPER: FPGA ARCHITECTURE DESIGN METHODOLOGY

Mike Hutton, 2006 .

Timing model reduction for hierarchical timing analysis

Yi Zhu, Shuo Zhou, Ronald L. Graham, 2006, ICCAD.

Session details: Expanding Rentian Analysis

Mike Hutton, 2002, SLIP '02.

Coping with uncertainty in FPGA architecture design

Mike Hutton, Boris Ratchev, David Mendel, 2005, International Conference on Field Programmable Logic and Applications, 2005..

Design of a high-density SoC FPGA at 20nm

Mike Hutton, Sean Atsatt, Brad Vest, 2014, 2014 IEEE Hot Chips 26 Symposium (HCS).

Efficient static timing analysis using a unified framework for false paths and multi-cycle paths

Yi Zhu, Shuo Zhou, Chung-Kuan Cheng, 2006, Asia and South Pacific Conference on Design Automation, 2006..

Equivalence Verification of FPGA and Structured ASIC Implementations

Mike Hutton, Jay Schleicher, Mihail Iotov, 2007, 2007 International Conference on Field Programmable Logic and Applications.

Characterization and parameterized generation of synthetic combinational benchmark circuits

J. P. Grossman, Jonathan Rose, Mike Hutton, 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Guest Editorial System-Level Interconnect Prediction

Mike Hutton, Joni Dambre, 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

FPGA Performance Optimization Via Chipwise Placement Considering Process Variations

Jinjun Xiong, Lei He, Mike Hutton, 2006, 2006 International Conference on Field Programmable Logic and Applications.

Stochastic Physical Synthesis Considering Prerouting Interconnect Uncertainty and Process Variation for FPGAs

Yan Lin, Lei He, Mike Hutton, 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

FPGA Synthesis and Physical Design

Vaughn Betz, Mike Hutton, 2009, Embedded Systems Design and Verification.

A Methodology for FPGA to Structured-ASIC Synthesis and Verification

Mike Hutton, Jay Schleicher, Gregg Baeckler, 2006, Proceedings of the Design Automation & Test in Europe Conference.

The Stratix II logic and routing architecture

Vaughn Betz, Jonathan Rose, David M. Lewis, 2005, FPGA '05.

Improving the efficiency of static timing analysis with false paths

Yi Zhu, Shuo Zhou, Chung-Kuan Cheng, 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..

Challenges and opportunities for low power FPGAs in nanometer technologies

Lei He, Steven J. E. Wilton, Tim Tuan, 2005, ISLPED '05.

Efficient Timing Analysis With Known False Paths Using Biclique Covering

Yi Zhu, Shuo Zhou, Chung-Kuan Cheng, 2007, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Placement rent exponent calculation methods, temporal behaviour and FPGA architecture evaluation

Mike Hutton, Joachim Pistorius, M. Hutton, 2003, SLIP '03.

Placement and Timing for FPGAs Considering Variations

Yan Lin, Lei He, Mike Hutton, 2006, 2006 International Conference on Field Programmable Logic and Applications.

Interconnect prediction for programmable logic devices

Mike Hutton, M. Hutton, 2001, SLIP '01.

Guest Editorial: TRETS Special Edition on the 15th International Symposium on FPGAs

André DeHon, Mike Hutton, 2008, TRETS.

The First 25 Years of the FPL Conference

Marco Platzner, Viktor K. Prasanna, Hideharu Amano, 2017, ACM Trans. Reconfigurable Technol. Syst..

Understanding How the New HyperFlex Architecture Enables Next-Generation High-Performance Systems

Mike Hutton, 2010 .

Understanding How the New Intel® HyperFlexTM FPGA Architecture Enables Next-Generation High-Performance Systems

Mike Hutton, 2017 .