T. Kishimoto

Title Pages / Table of Contents

T. Kishimoto, 1992 .

VLSI Packaging Technique Using Liquid-Cooled Channels

T. Kishimoto, T. Ohsaki, T. Kishimoto, 1986 .

The CANDLES Trigger System for the Study of Double Beta Decay of $^{48}{\rm Ca}$

T. Kishimoto, M. Nomachi, S. Ajimura, 2014, IEEE Transactions on Nuclear Science.

Sub-1 /spl mu/m/sup 2/ high density embedded SRAM technologies for 100 nm generation SOC and beyond

K. Eriguchi, T. Kishimoto, T. Inbe, 2002, 2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303).

Control of Carrier Collection Efficiency in n+p Diode with Retrograde Well and Epitaxial Layers

T. Kishimoto, Masahide Inuishi, Nishimura Tadashi, 1997 .

Soft error susceptibility and immune structures in dynamic random access memories (DRAMs) investigated by nuclear microprobes

T. Kishimoto, S. Satoh, Yoshikazu Ohno, 1996 .

Soft error improvement in SRAMs by ion implanted shallow well structure

T. Kishimoto, Madoka Takai, I. Ogawa, 2000, 2000 International Conference on Ion Implantation Technology Proceedings. Ion Implantation Technology - 2000 (Cat. No.00EX432).

Suppression of ion-induced charge collection against soft-error

T. Kishimoto, Y. Ohno, H. Sayama, 1996, Proceedings of 11th International Conference on Ion Implantation Technology.