Ruifeng Guo

发表

Concurrent execution of diagnostic fault simulation and equivalence identification during diagnostic test generation

Irith Pomeranz, Xiaoming Yu, Enamul Amyeen, 2003, Proceedings. 21st VLSI Test Symposium, 2003..

A fault diagnosis method for information systems based on weighted fault diagnosis tree

Ruifeng Guo, Liming Duan, Fenghai Wang, 2017, 2017 IEEE 19th International Conference on e-Health Networking, Applications and Services (Healthcom).

Fault Dictionary Based Scan Chain Failure Diagnosis

Ruifeng Guo, Wu-Tung Cheng, Yu Huang, 2007, 16th Asian Test Symposium (ATS 2007).

Speed-Path Debug Using At-Speed Scan Test Patterns

Wu-Tung Cheng, Ruifeng Guo, Kun-Han Tsai, 2009, 2009 14th IEEE European Test Symposium.

Survey of Scan Chain Diagnosis

Wu-Tung Cheng, Chien-Mo James Li, Ruifeng Guo, 2008, IEEE Design & Test of Computers.

Diagnose Multiple Stuck-at Scan Chain Faults

Wu-Tung Cheng, Ruifeng Guo, Yu Huang, 2008, 2008 13th European Test Symposium.

Enabling yield analysis with X-compact

Srikanth Venkataraman, Ruifeng Guo, Subhasish Mitra, 2005, IEEE International Conference on Test, 2005..

Enhancing Transition Fault Model for Delay Defect Diagnosis

Ruifeng Guo, Kun-Han Tsai, Wu-Tung Cheng, 2008, 2008 17th Asian Test Symposium.

A Dynamic Power Management Algorithm for Sporadic Tasks in Real-Time Embedded Systems

Ruifeng Guo, Hongliang Wang, Changyi Deng, 2016, 2016 IEEE Trustcom/BigDataSE/ISPA.

A Topology-Aware Relay Lookup Scheme for P2P VoIP System

Weimin Lei, Wei Zhang, Xiuwu Zhang, 2010, Int. J. Commun. Netw. Syst. Sci..

A fault simulation based test pattern generator for synchronous sequential circuits

Irith Pomeranz, Sudhakar M. Reddy, Ruifeng Guo, 1999, Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146).

Scan-Based Speed-Path Debug for a Microprocessor

Jing Wang, Jing Zeng, Wu-Tung Cheng, 2012, IEEE Design & Test of Computers.

On speeding-up vector restoration based static compaction of test sequences for sequential circuits

Irith Pomeranz, Sudhakar M. Reddy, Ruifeng Guo, 1998, Proceedings Seventh Asian Test Symposium (ATS'98) (Cat. No.98TB100259).

Diagnosis of Multiple Physical Defects Using Logic Fault Models

Sudhakar M. Reddy, Wu-Tung Cheng, Ruifeng Guo, 2010, 2010 19th IEEE Asian Test Symposium.

The Research on Real-Time Middleware for Open Architecture Controller

Hu Lin, Dong Yu, Ruifeng Guo, 2005, IEEE International Conference on Embedded and Real-Time Computing Systems and Applications.

A Robust Automated Scan Pattern Mismatch Debugger

Wu-Tung Cheng, Ruifeng Guo, Kun-Han Tsai, 2008, 2008 17th Asian Test Symposium.

Research on tool swept volume in NC simulation

Jie Li, Jiping Li, Ruifeng Guo, 2011, Proceedings of 2011 International Conference on Electronic & Mechanical Engineering and Information Technology.

On improving static test compaction for sequential circuits

Irith Pomeranz, Sudhakar M. Reddy, Ruifeng Guo, 2001, VLSI Design 2001. Fourteenth International Conference on VLSI Design.

An experimental study of N-detect scan ATPG patterns on a processor

Enamul Amyeen, Srikanth Venkataraman, Ruifeng Guo, 2004, 22nd IEEE VLSI Test Symposium, 2004. Proceedings..

Proptest: a property based test pattern generator for sequential circuits using test compaction

Irith Pomeranz, Sudhakar M. Reddy, Ruifeng Guo, 1999, DAC '99.

Diagnostic test generation for small delay defect diagnosis

Ruifeng Guo, Kun-Han Tsai, Wu-Tung Cheng, 2010, Proceedings of 2010 International Symposium on VLSI Design, Automation and Test.

Emulating and diagnosing IR-drop by using dynamic SDF

Mark Mohammad Tehranipoor, Wu-Tung Cheng, Ruifeng Guo, 2010, 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC).

At-Speed Scan Test Method for the Timing Optimization and Calibration

Wu-Tung Cheng, Ruifeng Guo, Kun-Han Tsai, 2009, 2009 Asian Test Symposium.

Efficient Cell-Aware Defect Characterization for Multi-bit Cells

Ruifeng Guo, Xiaolei Cai, Brian Archer, 2018, 2018 IEEE International Test Conference in Asia (ITC-Asia).

Accurate Modeling Method for Generalized Tool Swept Volume in 5-axis NC Machining Simulation

Jie Li, Ruifeng Guo, Zhixiang Shao, 2011, J. Softw..

Diagnosis of Multiple Faults Based on Fault-Tuple Equivalence Tree

Sudhakar M. Reddy, Wu-Tung Cheng, Xun Tang, 2011, 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems.

Evaluation of test metrics: stuck-at, bridge coverage estimate and gate exhaustive

Jinkyu Lee, Enamul Amyeen, Srikanth Venkataraman, 2006, 24th IEEE VLSI Test Symposium.

The effects of test compaction on fault diagnosis

Irith Pomeranz, Sudhakar M. Reddy, Ruifeng Guo, 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

Diagnosis and Layout Aware (DLA) Scan Chain Stitching

Yu Hu, Xiaowei Li, Jing Ye, 2015, IEEE Trans. Very Large Scale Integr. Syst..

An Effective RM-Based Scheduling Algorithm for Fault-Tolerant Real-Time Systems

Ruifeng Guo, Wanfu Ding, 2009, 2009 International Conference on Computational Science and Engineering.

A complete test set to diagnose scan chain failures

Wu-Tung Cheng, Ruifeng Guo, Yu Huang, 2007, 2007 IEEE International Test Conference.

Detection and Diagnosis of Static Scan Cell Internal Defect

Wu-Tung Cheng, Ruifeng Guo, Liyang Lai, 2008, 2008 IEEE International Test Conference.

Scan Chain Diagnosis by Adaptive Signal Profiling with Manufacturing ATPG Patterns

Wu-Tung Cheng, Ruifeng Guo, Yu Huang, 2009, 2009 Asian Test Symposium.

PROPTEST: a property-based test generator for synchronous sequential circuits

Irith Pomeranz, Sudhakar M. Reddy, Ruifeng Guo, 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Improve speed path identification with suspect path expressions

Wu-Tung Cheng, Jiun-Lang Huang, Manish Sharma, 2013, 2013 International Symposium onVLSI Design, Automation, and Test (VLSI-DAT).

Linking events-based communication mechanism in multi-agent systems

Ray Y. Zhong, Ruifeng Guo, Liming Duan, 2018, 2018 IEEE 15th International Conference on Networking, Sensing and Control (ICNSC).

A tool path error estimate in computer numerical control for five-axis machining

Han Zhang, Yiwen Zhang, Ruifeng Guo, 2013, 2013 Ninth International Conference on Natural Computation (ICNC).

Diagnose compound scan chain and system logic defects

Wu-Tung Cheng, Ruifeng Guo, Yu Huang, 2007, 2007 IEEE International Test Conference.

An algorithmic technique for diagnosis of faulty scan chains

Srikanth Venkataraman, Ruifeng Guo, 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Debugging clock-data race failures caused by vulnerable design

Ruifeng Guo, Wu-Tung Cheng, Yu Huang, 2008, 2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT).

A technique for fault diagnosis of defects in scan chains

Srikanth Venkataraman, Ruifeng Guo, S. Venkataraman, 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

On Improving Diagnostic Test Generation for Scan Chain Failures

Sudhakar M. Reddy, Wu-Tung Cheng, Xun Tang, 2009, 2009 Asian Test Symposium.

Static test compaction for synchronous sequential circuits based on vector restoration

Irith Pomeranz, Sudhakar M. Reddy, Ruifeng Guo, 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Enhancing the Success Rate of Primary Version While Guaranteeing Fault-Tolerant Capability for Real-Time Systems

Ruifeng Guo, Wanfu Ding, 2009, 2009 15th IEEE Pacific Rim International Symposium on Dependable Computing.

Improving the simulation efficiency in five-axis milling by using an advanced octree and an implicit formula of a generalized cutter

Ruifeng Guo, Hongliang Wang, R. Guo, 2013, J. Syst. Sci. Complex..

Material Removal Simulation of Multi-axis NC Milling Based on Spatial Partitioning Level of Detail Model

Xian Liu, Ruifeng Guo, Hongliang Wang, 2012, 2012 IEEE 12th International Conference on Computer and Information Technology.

Design and Evaluation of Sectional Real-Time Scheduling Algorithms Based on System Load

Ruifeng Guo, Wanfu Ding, 2008, 2008 The 9th International Conference for Young Computer Scientists.

Improving compressed test pattern generation for multiple scan chain failure diagnosis

Sudhakar M. Reddy, Wu-Tung Cheng, Xun Tang, 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

Reverse-order-restoration-based static test compaction for synchronous sequential circuits

Irith Pomeranz, Sudhakar M. Reddy, Ruifeng Guo, 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Diagnosis and Layout Aware (DLA) scan chain stitching

Yu Hu, Xiaowei Li, Jing Ye, 2013, 2013 IEEE International Test Conference (ITC).

Using Scan-Dump Values to Improve Functional-Diagnosis Methodology

Michael S. Hsiao, Kai Yang, Vishnu C. Vimjam, 2007, 25th IEEE VLSI Test Symposium (VTS'07).