Karem A. Sakallah

发表

Analysis and design of latch-controlled synchronous digital circuits

Kunle Olukotun, Trevor N. Mudge, Karem A. Sakallah, 1990, DAC '90.

Generic ILP versus specialized 0-1 ILP: an update

Igor L. Markov, Karem A. Sakallah, Fadi A. Aloul, 2002, IEEE/ACM International Conference on Computer Aided Design, 2002. ICCAD 2002..

Fast and accurate timing characterization using functionalinformation

John P. Hayes, Hakan Yalcin, Cyrus Bamji, 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

An approximate timing analysis method for datapath circuits

John P. Hayes, Hakan Yalcin, Karem A. Sakallah, 1996, ICCAD 1996.

Maximum rate single-phase clocking of a closed pipeline including wave pipelining, stoppability, and startability

Edward S. Davidson, Karem A. Sakallah, Chuan-Hua Chang, 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Improved Design Debugging Using Maximum Satisfiability

Sean Safarpour, Andreas G. Veneris, Karem A. Sakallah, 2007, Formal Methods in Computer Aided Design (FMCAD'07).

Constructive multi-level synthesis by way of functional properties

Karem A. Sakallah, Victor N. Kravets, 2001 .

Generalizing Core-Guided Max-SAT

Karem A. Sakallah, Mark H. Liffiton, 2009, SAT.

The edge-based design rule model revisited

Karem A. Sakallah, Michael A. Riepe, K. Sakallah, 1998, TODE.

Satisfiability models and algorithms for circuit delay computation

Joao Marques-Silva, Luís Miguel Silveira, Karem A. Sakallah, 2002, TODE.

Graph Symmetry Detection and Canonical Labeling: Differences and Synergies pdf

Igor L. Markov, Karem A. Sakallah, Hadi Katebi, 2012, Turing-100.

SAMSON2: An Event Driven VLSI Circuit Simulator

Karem A. Sakallah, Stephen W. Director, S. W. Director, 1985, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Identifying Conflicts in Overconstrained Temporal Problems

Martha E. Pollack, Karem A. Sakallah, Michael D. Moffitt, 2005, IJCAI.

Search-based SAT using zero-suppressed BDDs

Karem A. Sakallah, Fadi A. Aloul, Maher N. Mneimneh, 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

Principles of sequential-equivalence verification

Karem A. Sakallah, Maher N. Mneimneh, K. Sakallah, 2005, IEEE Design & Test of Computers.

Static timing analysis

Karem A. Sakallah, Yuji Kukimoto, Michel Berkelaar, 2001 .

Constructive library-aware synthesis using symmetries

Karem A. Sakallah, Victor N. Kravets, 2000, DATE '00.

On applying incremental satisfiability to delay fault testing

Joao Marques-Silva, Karem A. Sakallah, Joonyoung Kim, 2000, DATE '00.

Reveal: A Formal Verification Tool for Verilog Designs

Karem A. Sakallah, Mark H. Liffiton, Zaher S. Andraus, 2008, LPAR.

Ario: A Linear Integer Arithmetic Logic Solver

Karem A. Sakallah, Hossein M. Sheini, 2006, 2006 Formal Methods in Computer Aided Design.

sub-SAT: a formulation for relaxed boolean satisfiability with applications in routing

Rob A. Rutenbar, Karem A. Sakallah, Hui Xu, 2003, ISPD '02.

A New FPGA Detailed Routing Approach Via

Rob A. Rutenbar, Karem A. Sakallah, Gi-Joon Nam, 2002 .

Breaking instance-independent symmetries in exact graph coloring

Igor L. Markov, Karem A. Sakallah, Fadi A. Aloul, 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

A comparative study of two Boolean formulations of FPGA detailed routing constraints

Rob A. Rutenbar, Gi-Joon Nam, Karem A. Sakallah, 2001, IEEE Transactions on Computers.

Distilling critical attack graph surface iteratively through minimum-cost SAT solving

Atul Prakash, Xinming Ou, Su Zhang, 2011, ACSAC '11.

Satisfiability-based detailed FPGA routing

Rob A. Rutenbar, Gi-Joon Nam, Karem A. Sakallah, 1999, Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013).

AMUSE: a minimally-unsatisfiable subformula extractor

Igor L. Markov, Karem A. Sakallah, Yoonna Oh, 2004, Proceedings. 41st Design Automation Conference, 2004..

An experimental study of satisfiability search heuristics (poster paper)

Joao Marques-Silva, Karem A. Sakallah, Fadi A. Aloul, 2000, DATE '00.

SMT(CLU): a step toward scalability in system verification

Karem A. Sakallah, Hossein M. Sheini, 2006, ICCAD.

Invited Tutorial: Boolean Satisfiability Algorithms and Applications in Electronic Design Automation

Joao Marques-Silva, Karem A. Sakallah, 2000, CAV.

Resynthesis of multi-level circuits under tight constraints using symbolic optimization

Karem A. Sakallah, Victor N. Kravets, 2002, ICCAD 2002.

Critical paths in circuits with level-sensitive latches

Trevor N. Mudge, Karem A. Sakallah, Timothy M. Burks, 1995, IEEE Trans. Very Large Scale Integr. Syst..

Using constraint geometry to determine maximum rate pipeline clocking

Edward S. Davidson, Karem A. Sakallah, Chuan-Hua Chang, 1992, ICCAD.

SAT-based sequential depth computation

Karem A. Sakallah, Maher N. Mneimneh, 2003, ASP-DAC '03.

An advanced timing characterization method using mode dependecy

John P. Hayes, Hakan Yalcin, Cyrus Bamji, 2001, DAC '01.

Macromodel simplification using dimensional analysis

Ayman I. Kayssi, Karem A. Sakallah, 1994, Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94.

Dynamic symmetry-breaking for improved Boolean optimization

Igor L. Markov, Karem A. Sakallah, Fadi A. Aloul, 2005, ASP-DAC.

Theory and Applications of Satisfiability Testing - SAT 2011 - 14th International Conference, SAT 2011, Ann Arbor, MI, USA, June 19-22, 2011. Proceedings

Karem A. Sakallah, Laurent Simon, K. Sakallah, 2011, SAT.

Delay macromodels for point-to-point MCM interconnections

Karem A. Sakallah, Ayman Kayssi, 1992, Proceedings 1992 IEEE Multi-Chip Module Conference MCMC-92.

A 160000 transistor GaAs microprocessor

Trevor Mudge, Richard B. Brown, R. J. Lomax, 1993, 1993 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

From Propositional Satisfiability to Satisfiability Modulo Theories

Karem A. Sakallah, Hossein M. Sheini, K. Sakallah, 2006, SAT.

Conflict analysis in search algorithms for satisfiability

Joao Marques-Silva, Karem A. Sakallah, K. Sakallah, 1996, Proceedings Eighth IEEE International Conference on Tools with Artificial Intelligence.

Timing models for gallium arsenide direct-coupled FET logic circuits

Ayman I. Kayssi, Karem A. Sakallah, 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Optimal Combinational Multi-Level Logic Synthesis

Karem A. Sakallah, Elizabeth Ann Ernst, E. A. Ernst, 2009 .

SATIRE: A new incremental satisfiability engine

Joonyoung Kim, Karem A. Sakallah, Jesse Whittemore, 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

Conflict Anticipation in the Search for Graph Automorphisms

Igor L. Markov, Karem A. Sakallah, Hadi Katebi, 2012, LPAR.

Delay macromodels for point-to-point MCM interconnections

Karem A. Sakallah, Ayman Kayssi, 1994 .

Ravel: assigned-delay compiled-code logic simulation

Karem A. Sakallah, Emily J. Shriver, 1992, ICCAD.

Delay modeling for functional timing analysis

Karem A. Sakallah, V. Chandramouli, 1998 .

Robust SAT-Based Search Algorithm for Leakage Power Reduction

David Blaauw, Soha Hassoun, Karem A. Sakallah, 2002, PATMOS.

On Solving Soft Temporal Constraints Using SAT Techniques

Martha E. Pollack, Karem A. Sakallah, Bart Peintner, 2005, CP.

Conflict Analysis and Branching Heuristics in the Search for Graph Automorphisms

Igor L. Markov, Karem A. Sakallah, Hadi Katebi, 2013, 2013 IEEE 25th International Conference on Tools with Artificial Intelligence.

Satometer:: how much have we searched?

Karem A. Sakallah, Fadi A. Aloul, Brian D. Sierawski, 2002, DAC '02.

Functional timing analysis for IP characterization

Hakan Yalcin, Cyrus Bamji, Karem A. Sakallah, 1999, DAC '99.

PBS: A Backtrack-Search Pseudo-Boolean Solver and Optimizer

Igor L. Markov, Karem A. Sakallah, Fadi A. Aloul, 2000 .

ShatterPB: symmetry-breaking for pseudo-boolean formulas

Igor L. Markov, Karem A. Sakallah, Fadi A. Aloul, 2004, ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753).

Efficient symmetry breaking for Boolean satisfiability

Igor L. Markov, Karem A. Sakallah, Fadi A. Aloul, 2003, IEEE Transactions on Computers.

Proceedings of the 14th international conference on Theory and application of satisfiability testing

Karem A. Sakallah, Laurent Simon, 2011 .

Report on the SAT 2007 Conference on Theory and Applications of Satisfiability Testing

Inês Lynce, Joao Marques-Silva, Karem A. Sakallah, 2007, AI Mag..

euforia: Complete Software Model Checking with Uninterpreted Functions

Karem A. Sakallah, Denis Bueno, K. Sakallah, 2019, VMCAI.

Anatomy and Empirical Evaluation of Modern SAT Solvers

Joao Marques-Silva, Karem A. Sakallah, 2011, Bull. EATCS.

Exploiting structure in symmetry detection for CNF

Igor L. Markov, Karem A. Sakallah, Mark H. Liffiton, 2004, Proceedings. 41st Design Automation Conference, 2004..

Solution and Optimization of Systems of Pseudo-Boolean Constraints

Igor L. Markov, Karem A. Sakallah, Fadi A. Aloul, 2007, IEEE Transactions on Computers.

A new FPGA detailed routing approach via search-based Booleansatisfiability

Rob A. Rutenbar, Gi-Joon Nam, Karem A. Sakallah, 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

MINCE: A Static Global Variable-Ordering Heuristic for SAT Search and BDD Manipulation

Igor L. Markov, Karem A. Sakallah, Fadi A. Aloul, 2004, J. Univers. Comput. Sci..

Optimization Of Critical Paths In Circuits With Level-sensitive Latches

Karem A. Sakallah, Timothy Michael Burks, K. Sakallah, 1992, IEEE/ACM International Conference on Computer-Aided Design.

M32: a constructive multilevel logic synthesis system

Karem A. Sakallah, Victor N. Kravets, 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

I4: incremental inference of inductive invariants for verification of distributed protocols

Jean-Baptiste Jeannin, Karem A. Sakallah, Baris Kasikci, 2019, SOSP.

Delay macromodels for the timing analysis of GaAs DCFL

Ayman I. Kayssi, Karem A. Sakallah, K. Sakallah, 1992, Proceedings EURO-DAC '92: European Design Automation Conference.

ZBDD-Based Backtrack Search SAT Solver

Karem A. Sakallah, Fadi A. Aloul, Maher N. Mneimneh, 2002, IWLS.

Modeling the effects of temporal proximity of input transitions on gate propagation delay and transition time

Karem A. Sakallah, V. Chandramouli, 1996, DAC '96.

Robust search algorithms for test pattern generation

Joao Marques-Silva, Karem A. Sakallah, K. Sakallah, 1997, Proceedings of IEEE 27th International Symposium on Fault Tolerant Computing.

Model Checking of Verilog RTL Using IC3 with Syntax-Guided Abstraction

Aman Goel, Karem A. Sakallah, 2019, NFM.

Clock qualification algorithm for timing analysis of custom CMOS VLSI circuits with overlapped clocking disciplines and on-section clock derivation

Karem A. Sakallah, Somanathan C. Menon, 1990, Systems Integration '90. Proceedings of the First International Conference on Systems Integration.

Dynamic Path Reduction for Software Model Checking

Radu Grosu, Scott A. Smolka, Karem A. Sakallah, 2009, IFM.

Satometer: How Much Have We Searched? (Preprint)

Karem A. Sakallah, Fadi A. Aloul, Brian D. Sierawski, 2002 .

Solving difficult instances of Boolean satisfiability in the presence of symmetry

Igor L. Markov, Karem A. Sakallah, Fadi A. Aloul, 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

A Boolean satisfiability-based incremental rerouting approach with application to FPGAs

Rob A. Rutenbar, Gi-Joon Nam, Karem A. Sakallah, 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.

Delay modeling for GaAs DCFL circuits

Karem A. Sakallah, Ayman Kayssi, A. I. Kayssi, 1993, 15th Annual GaAs IC Symposium.

Improving the efficiency of circuit-to-BDD conversion by gate and input ordering

Igor L. Markov, Karem A. Sakallah, Fadi A. Aloul, 2002, Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors.

CheckT/sub c/ and minT/sub c/: timing verification and optimal clocking of synchronous digital circuits

Trevor N. Mudge, Karem A. Sakallah, Kunle Olukotun, 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

Simultaneous switching noise in printed circuit boards

Linda P. B. Katehi, Karem A. Sakallah, 1993 .

Test Pattern Generation for Circuits Using Power Management Techniques

Karem A. Sakallah, Joao P. Marques Silva, Jose C. Monteiro, 1997 .

TIMING, TEST AND MANUFACTURING OVERVIEW

Sani R. Nassif, Karem A. Sakallah, Duncan M. Walker, 2003 .

Timing abstraction of intellectual property blocks

Karem A. Sakallah, Mohammad Mortazavi, Robert Palermo, 1997, Proceedings of CICC 97 - Custom Integrated Circuits Conference.

Ravel: assinged-delay compiled-code logic simulation

Karem A. Sakallah, Emily Shriver, 1992, 1992 IEEE/ACM International Conference on Computer-Aided Design.

Computation of switching noise in PCBs for digital packages

Jong-Gwan Yook, Karem A. Sakallah, V. Chandramouli, 1995, Proceedings of Electrical Performance of Electronic Packaging.

Satometer: how much have we searched?

Karem A. Sakallah, Fadi A. Aloul, Brian D. Sierawski, 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Faster symmetry discovery using sparsity of symmetries

Igor L. Markov, Karem A. Sakallah, Paul T. Darga, 2008, 2008 45th ACM/IEEE Design Automation Conference.

Timing Analysis of Domino Logic

Trevor Mudge, Karem A. Sakallah, David Van Campenhout, 1996 .

Transistor placement for noncomplementary digital VLSI cell synthesis

Karem A. Sakallah, Michael A. Riepe, K. Sakallah, 2003, TODE.

FORCE: a fast and easy-to-implement variable-ordering heuristic

Igor L. Markov, Karem A. Sakallah, Fadi A. Aloul, 2003, GLSVLSI '03.

Application of system-level EM modeling to high-speed digital IC packages and PCBs

Linda P. B. Katehi, Jong-Gwan Yook, Karem A. Sakallah, 1997 .

System level EM modeling of digital IC packages and PC boards

Jong-Gwan Yook, Karem A. Sakallah, Linda P. B. Katehi, 1996 .

Searching for Autarkies to Trim Unsatisfiable Clause Sets

Karem A. Sakallah, Mark H. Liffiton, 2008, SAT.

The impact of signal transition time on path delay computation

Trevor Mudge, Karem A. Sakallah, Ayman Kayssi, 1993 .

Identification of critical paths in circuits with level-sensitive latches

Trevor N. Mudge, Karem A. Sakallah, Timothy M. Burks, 1992, ICCAD.

AFTA: A formal delay model for functional timing analysis

Karem A. Sakallah, V. Chandramouli, Jesse Whittemore, 1998, Proceedings Design, Automation and Test in Europe.

Satisfiability-based layout revisited: detailed routing of complex FPGAs via search-based Boolean SAT

Rob A. Rutenbar, Gi-Joon Nam, Karem A. Sakallah, 1999, FPGA '99.

Symmetry breaking for pseudo-Boolean formulas

Igor L. Markov, Karem A. Sakallah, Fadi A. Aloul, 2008, JEAL.

Session details: Formal verification: theory and practice

Karem A. Sakallah, Yuan Lu, 2005, ASP-DAC '05.

GaAs RISC processors

Trevor Mudge, Richard B. Brown, R. J. Lomax, 1992, GaAs IC Symposium Technical Digest 1992.

Synchronization of pipelines

Trevor N. Mudge, Edward S. Davidson, Karem A. Sakallah, 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Automatic Formal Verification of Control Logic in Hardware Designs

Karem A. Sakallah, Zaher S. Andraus, 2009 .

Automatic abstraction and verification of verilog models

Karem A. Sakallah, Zaher S. Andraus, K. Sakallah, 2004, Proceedings. 41st Design Automation Conference, 2004..

GRASP: A Search Algorithm for Propositional Satisfiability

Joao Marques-Silva, Karem A. Sakallah, K. Sakallah, 1999, IEEE Trans. Computers.

Faster SAT and smaller BDDs via common function structure

Igor L. Markov, Karem A. Sakallah, Fadi A. Aloul, 2001, IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281).

Computing Vertex Eccentricity in Exponentially Large Graphs: QBF Formulation and Solution

Karem A. Sakallah, Maher N. Mneimneh, K. Sakallah, 2003, SAT.

Proceedings 8th International Workshop on Verification and Program Transformation and 7th Workshop on Horn Clauses for Verification and Synthesis: Horn2VMT: Translating Horn Reachability into Transition Systems

Karem A. Sakallah, Denis Bueno, 2020 .

A Progressive Simplifier for Satisfiability Modulo Theories

Karem A. Sakallah, Hossein M. Sheini, K. Sakallah, 2006, SAT.

Congestion driven quadratic placement

Richard B. Brown, Karem A. Sakallah, Phiroze N. Parakh, 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

Generating Data Race Witnesses by an SMT-Based Analysis

Chao Wang, Zijiang Yang, Karem A. Sakallah, 2011, NASA Formal Methods.

Solving difficult SAT instances in the presence of symmetry

Igor L. Markov, Karem A. Sakallah, Fadi A. Aloul, 2002, Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324).

Dynamic Search-Space Pruning Techniques in Path Sensitization

Joao Marques-Silva, Karem A. Sakallah, K. Sakallah, 1994, 31st Design Automation Conference.

Analysis and design of latch-controlled synchronous digital circuits

Kunle Olukotun, Trevor N. Mudge, Karem A. Sakallah, 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Generalized symmetries in Boolean functions

Karem A. Sakallah, Victor N. Kravets, 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

Overview of complementary GaAs technology for high-speed VLSI circuits

Trevor N. Mudge, Richard B. Brown, Karem A. Sakallah, 1998, IEEE Trans. Very Large Scale Integr. Syst..

Hybrid Routing for FPGAs by Integrating Boolean Satisfiability with Geometric Search

Rob A. Rutenbar, Gi-Joon Nam, Karem A. Sakallah, 2002, FPL.

A comparative study of two Boolean formulations of FPGA detailed routing constraints

Rob A. Rutenbar, Gi-Joon Nam, Karem A. Sakallah, 2001, ISPD '01.

Majority-Based Decomposition of Carry Logic in Binary Adders

Leyla Nazhandali, Karem A. Sakallah, 2002, IWLS.

Preserving synchronizing sequences of sequential circuits after retiming

Karem A. Sakallah, John Moondanos, Maher Mneimneh, 2004 .

On Finding All Minimally Unsatisfiable Subformulas

Karem A. Sakallah, Mark H. Liffiton, K. Sakallah, 2005, SAT.

Pueblo: a modern pseudo-Boolean SAT solver

Karem A. Sakallah, Hossein M. Sheini, 2005, Design, Automation and Test in Europe.

Satisfiability-Based Functional Delay Fault Testing

Joao Marques-Silva, Karem A. Sakallah, Joonyoung Kim, 1999, VLSI.

A branch and bound algorithm for extracting smallest minimal unsatisfiable subformulas

Inês Lynce, Joao Marques-Silva, Karem A. Sakallah, 2008, Constraints.

A Scalable Method for Solving Satisfiability of Integer Linear Arithmetic Logic

Karem A. Sakallah, Hossein M. Sheini, K. Sakallah, 2005, SAT.

Symmetry and Satisfiability

Karem A. Sakallah, K. Sakallah, 2021, Handbook of Satisfiability.

axirnurn ate Single-phase C1 losed Pipeline including ipelining, S toppability , and S t

Edward S. Davidson, Karem A. Sakallah, Chuan-Hua Chang, 1995 .

A first-order charge conserving MOS capacitance model

Karem A. Sakallah, Yao-Tsung Yen, Steve S. Greenberg, 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

A Branch-and-Bound Algorithm for Extracting Smallest Minimal Unsatisfiable Formulas

Inês Lynce, Joao Marques-Silva, Karem A. Sakallah, 2005, SAT.

Detecting Traditional Packers, Decisively

Karem A. Sakallah, Michael Bailey, Kevin J. Compton, 2013, RAID.

Transistor level micro-placement and routing for two-dimensional digital VLSI cell synthesis

Karem A. Sakallah, Michael A. Riepe, K. Sakallah, 1999, ISPD '99.

The Aurora RAM Compiler

Richard B. Brown, Karem A. Sakallah, Ajay Chandna, 1995, 32nd Design Automation Conference.

Incorporating user control in automated interactive scheduling systems

Jina Huh, Martha E. Pollack, Karem A. Sakallah, 2010, Conference on Designing Interactive Systems.

Pueblo: A Hybrid Pseudo-Boolean SAT Solver

Karem A. Sakallah, Hossein M. Sheini, K. Sakallah, 2006, J. Satisf. Boolean Model. Comput..

Scalable hybrid verification of complex microprocessors

Todd M. Austin, Karem A. Sakallah, Fadi A. Aloul, 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

Improved Design Debugging Using Maximum Satisfiability

Sean Safarpour, Andreas Veneris, Karem A. Sakallah, 2007 .

Min-max linear programming and the timing analysis of digital circuits

Karem A. Sakallah, Timothy M. Burks, 1993, ICCAD.

Analytical transient response of CMOS inverters

Karem A. Sakallah, Ayman Kayssi, Timothy Michael Burks, 1992 .

On solving stack-based incremental satisfiability problems

Joonyoung Kim, Karem A. Sakallah, Jesse Whittemore, 2000, Proceedings 2000 International Conference on Computer Design.

AVR: Abstractly Verifying Reachability

Aman Goel, Karem A. Sakallah, K. Sakallah, 2020, TACAS.

Unbounded Scalable Verification Based on Approximate Property-Directed Reachability and Datapath Abstraction

Karem A. Sakallah, Suho Lee, K. Sakallah, 2014, CAV.

Theory and Applications of Satisfiability Testing - SAT 2007, 10th International Conference, Lisbon, Portugal, May 28-31, 2007, Proceedings

Joao Marques-Silva, Karem A. Sakallah, 2007, SAT.

A SAT-Based Decision Procedure for Mixed Logical/Integer Linear Problems

Karem A. Sakallah, Hossein M. Sheini, 2005, CPAIOR.

Computation of switching noise in printed circuit boards

Linda P. B. Katehi, Jong-Gwan Yook, Karem A. Sakallah, 1997 .

Timing verification of sequential dynamic circuits

Trevor N. Mudge, Karem A. Sakallah, David Van Campenhout, 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Ravel-XL: a hardware accelerator for assigned-delay compiled-code logic gate simulation

Joao Marques-Silva, Richard B. Brown, Karem A. Sakallah, 1996, IEEE Trans. Very Large Scale Integr. Syst..

System Level E odeli gital IC Packages and PC

Jong-Gwan Yook, Karem A. Sakallah, Tawfik Arabi, 1996 .

Algorithms for Computing Minimal Unsatisfiable Subsets of Constraints

Karem A. Sakallah, Mark H. Liffiton, K. Sakallah, 2007, Journal of Automated Reasoning.

Empirical Study of the Anatomy of Modern Sat Solvers

Joao Marques-Silva, Karem A. Sakallah, Hadi Katebi, 2011, SAT.

The design of a microsupercomputer

Ayman I. Kayssi, Kunle Olukotun, Trevor N. Mudge, 1991, Computer.

Efficient and robust test generation-based timing analysis

Joao Marques-Silva, Karem A. Sakallah, K. Sakallah, 1994, Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94.

Refinement strategies for verification methods based on datapath abstraction

Karem A. Sakallah, Mark H. Liffiton, Zaher S. Andraus, 2006, Asia and South Pacific Conference on Design Automation, 2006..

Ravel-XL: a hardware accelerator for assigned-delay compiled-code logic gate simulation

Joao Marques-Silva, Richard B. Brown, Karem A. Sakallah, 1993, Proceedings of 1993 IEEE International Conference on Computer Design ICCD'93.

GRASP-A new search algorithm for satisfiability

Joao Marques-Silva, Karem A. Sakallah, K. Sakallah, 1996, Proceedings of International Conference on Computer Aided Design.

Efficient Gate and Input Ordering for Circuit-to-BDD Conversion

Igor L. Markov, Karem A. Sakallah, Fadi A. Aloul, 2002, IWLS.

An analysis of path sensitization criteria

Joao Marques-Silva, Karem A. Sakallah, K. Sakallah, 1993, Proceedings of 1993 IEEE International Conference on Computer Design ICCD'93.

Optimization of critical paths in circuits with level-sensitive latches

Karem A. Sakallah, Timothy M. Burks, 1994, ICCAD.

Symmetry and Satisfiability: An Update

Igor L. Markov, Karem A. Sakallah, Hadi Katebi, 2010, SAT.

An approximate timing analysis method for datapath circuits

John P. Hayes, Hakan Yalcin, Karem A. Sakallah, 1996, Proceedings of International Conference on Computer Aided Design.

Generalized Boolean symmetries through nested partition refinement

Igor L. Markov, Karem A. Sakallah, Hadi Katebi, 2013, 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Boolean satisfiability in electronic design automation

Joao Marques-Silva, Karem A. Sakallah, 2000, Proceedings 37th Design Automation Conference.

Dynamic symmetry-breaking for Boolean satisfiability

Igor L. Markov, Karem A. Sakallah, Fadi A. Aloul, 2009, Annals of Mathematics and Artificial Intelligence.

Timing verification of sequential domino circuits

Trevor N. Mudge, Karem A. Sakallah, David Van Campenhout, 1996, Proceedings of International Conference on Computer Aided Design.

Towards Automatic Inference of Inductive Invariants

Jean-Baptiste Jeannin, Aman Goel, Karem A. Sakallah, 2019, HotOS.

Shatter: efficient symmetry-breaking for Boolean satisfiability

Igor L. Markov, Karem A. Sakallah, Fadi A. Aloul, 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

GRASP—a new search algorithm for satisfiability

Karem A. Sakallah, Joao P. Marques Silva, 1996, ICCAD 1996.

Preserving synchronizing sequences of sequential circuits after retiming

Karem A. Sakallah, John Moondanos, Maher N. Mneimneh, 2004, ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753).

Trace-Driven Verification of Multithreaded Programs

Zijiang Yang, Karem A. Sakallah, K. Sakallah, 2010, ICFEM.

Invited Talk: AVR: Word-Level Verification by Equality Abstraction of Data State

Karem A. Sakallah, 2021, SMT.

On Symmetry and Quantification: A New Approach to Verify Distributed Protocols.

Karem A. Sakallah, Aman Goel, K. Sakallah, 2021 .

On Symmetry and Quantification: A New Approach to Verify Distributed Protocols pdf

Karem A. Sakallah, Aman Goel, K. Sakallah, 2021, NFM.

Using constraint geometry to determine maximum rate pipeline clocking

Edward S. Davidson, Karem A. Sakallah, Chuan-Hua Chang, 1992, 1992 IEEE/ACM International Conference on Computer-Aided Design.

Breaking instance-independent symmetries in exact graph coloring

Igor L. Markov, Karem A. Sakallah, Fadi A. Aloul, 2004 .