Koichiro Mashiko

发表

A High Speed Wide Band SRAM Macro using Complementary Half-Swing Bus Architecture

Tadashi Sumi, Yasunobu Nakase, Harufusa Kondo, 1996, ESSCIRC '96: Proceedings of the 22nd European Solid-State Circuits Conference.

Influences of circuit design on the characteristics of soft error in MOS dynamic RAMs

Koichiro Mashiko, Yasuji Nagayama, Tsutomu Yoshihara, 1983 .

A 47ns 64KW × 4b CMOS DRAM with relaxed timing requirements

K. Arimoto, Koichiro Mashiko, Toshifumi Kobayashi, 1986, 1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

A high-speed 64K/spl times/4 CMOS DRAM using on-chip self-timing techniques

K. Arimoto, Koichiro Mashiko, T. Nakano, 1986 .

A voltage compensated series-gate bipolar circuit operating at sub-2 V

Koichiro Mashiko, H. Sato, K. Ueda, 1993 .

A 1.8 V 2.5 GHz PLL using 0.18 /spl mu/m SOI/CMOS technology

Koichiro Mashiko, Yoshio Matsuda, K. Ueda, 1999, 1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345).

Session details: Analysis and simulation techniques

Koichiro Mashiko, Richard Shi, 2005, ASP-DAC '05.

le Chip I

Tadashi Sumi, Koichiro Mashiko, Hisayasu Sato, 1996 .

A Design of High-Speed 4-2 Compressor for Fast Multiplier (Special Issue on Ultra-High-Speed LSIs)

Hiroaki Suzuki, Tadashi Sumi, Hiroshi Makino, 1996 .

Leading-zero anticipatory logic for high-speed floating point addition

Koichiro Mashiko, T. Sumi, H. Suzuki, 1995 .

A 2-ns 16K bipolar ECL RAM with reduced word-line voltage swing

Yasunobu Nakase, Koichiro Mashiko, S. Kayano, 1991 .

A 300 MHz Dual Port Palette RAM Using Port Swap Architecture

Yasunobu Nakase, Koichiro Mashiko, Takeshi Tokuda, 1998 .

A fully compensated active pull-down ECL circuit with self-adjusting driving capability

Koichiro Mashiko, H. Sato, K. Ueda, 1996 .

SP 24.3: A 300MHz Dual Port Graphics RAM using Port Swap Architecture

Yasunobu Nakase, Koichiro Mashiko, Takeshi Tokuda, 1997 .

A built-in Hamming code ECC circuit for DRAMs

K. Arimoto, Koichiro Mashiko, Toshifumi Kobayashi, 1989 .

High-Speed Continuous-Time Subsampling Bandpass DeltaSigmaAD Modulator Architecture Employing Radio Frequency DAC

Toshiro Tsukada, Haruo Kobayashi, Koichiro Mashiko, 2006, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Test Pattern Considerations for Fault Tolerant High Density DRAM

Kazutami Arimoto, Koichiro Mashiko, Michihiro Yamada, 1985, ITC.

A bipolar-PMOS merged basic cell for 0.8 mu m BiCMOS sea of gates

Koichiro Mashiko, M. Hatanaka, K. Higashitani, 1991 .

A 3.6-Gb/s 340-mW 16:1 pipe-lined multiplexer using 0.18 m SOI-CMOS technology

Toru Nakura, Koichiro Mashiko, Tsutomu Yoshihara, 2000 .

A 336-neuron, 28 K-synapse, self-learning neural network chip with branch-neuron-unit architecture

Koichiro Mashiko, A. Maeda, S. Kayano, 1991 .

A 2.6-ns 64-b Fast and Small CMOS Adder (Special Issue on Ultra-High-Speed LSIs)

Hiroaki Suzuki, Tadashi Sumi, Hiroshi Makino, 1996 .

A speed-enhanced DRAM array architecture with embedded ECC

Masaki Tsukude, Kazuyasu Fujishima, K. Arimoto, 1990 .

A self-learning neural network chip with 125 neurons and 10 K self-organization synapses

S. Kayano, Koichiro Mashiko, T. Yamada, 1990 .

A floating-point divider using redundant binary circuits and an asynchronous clock scheme

Hiroaki Suzuki, Hiroshi Makino, Koichiro Mashiko, 1997, Proceedings International Conference on Computer Design VLSI in Computers and Processors.

How to design low-power digital cellular phones

Koichiro Mashiko, 1996, Proceedings of 1996 International Symposium on Low Power Electronics and Design.

A 64 bit carry look-ahead CMOS adder using Modified Carry Select

H. Suzuki, Hiroshi Makino, Koichiro Mashiko, 1995, Proceedings of the IEEE 1995 Custom Integrated Circuits Conference.

Floating-body effects on propagation delay in SOI/CMOS LSIs

Tadashi Sumi, Koichiro Mashiko, Hiroyuki Morinaka, 1996, 1996 IEEE International SOI Conference Proceedings.

An efficient screening method for DRAM memory cell capacitor dielectric

Koichiro Mashiko, Michihiro Yamada, Kiyohiro Furutani, 1990 .

Substrate bias voltage generator on dynamic MOS RAM chip

Kazuyasu Fujishima, Koichiro Mashiko, Michihiro Yamada, 1981 .

Session details: RF circuit design and design methodology

Koichiro Mashiko, Wing Hung Ki, 2005, ASP-DAC '05.

Silicon implementation of self-learning neural networks

Keisuke Okada, Koichiro Mashiko, S. Kayano, 1991, 1991., IEEE International Sympoisum on Circuits and Systems.

SOI/CMOS Circuit design for high-speed communication lsis

Koichiro Mashiko, Shigenobu Maeda, K. Ueda, 1997 .

Suppression of delay time instability on frequency using field shield isolation technology for deep sub-micron SOI circuits

Koichiro Mashiko, K. Ueda, Y. Inoue, 1996, International Electron Devices Meeting. Technical Digest.

How to design low-power digital cellular phones

Koichiro Mashiko, 1996, ISLPED '96.

Impact of 0.18 /spl mu/m SOI CMOS technology using hybrid trench isolation with high resistivity substrate on embedded RF/analog applications

T. Iwamatsu, Koichiro Mashiko, Masahide Inuishi, 2000, 2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104).

Academia-industry collaboration in SoC design education: wishes and reality

Koichiro Mashiko, Ki-Won Lee, A. Kanuma, 2004 .

Access time analysis of dynamic MOS RAM

Koichiro Mashiko, Yasuji Nagayama, Tsutomu Yoshihara, 1983 .

Comments on "Leading-zero anticipatory logic for high-speed floating point addition" [with reply]

Tadashi Sumi, Hiroshi Makino, Yasunobu Nakase, 1997 .

A BiCMOS wired-OR logic

H. Makino, H. Suzuki, Koichiro Mashiko, 1995 .

A Complementary Half-Swing Bus Architecture and its Application for Wide Band SRAM Macro

Yasunobu Nakase, Harufusa Kondo, Koichiro Mashiko, 1997 .

A 64-bit carry look ahead adder using pass transistor BiCMOS gates

H. Suzuki, Koichiro Mashiko, H. Shinohara, 1996, IEEE J. Solid State Circuits.

A 90ns 4Mb DRAM in a 300 mil DIP

Koichiro Mashiko, T. Yoshihara, T. Nakano, 1987, 1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

SP 21.2: A 1.9GHz Single-Chip IF Transceiver for Digital Cordless Phones

Koichiro Mashiko, Hisayasu Sato, Kazuhito Niwano, 1996 .

3. Ogb/s, 272mw, 8:1 Multiplexer And 4.1gb/s, 388mw, 1:8 Demultiplexer

S. Kubo, Koichiro Mashiko, H. Sato, 1994, Proceedings of 1994 IEEE Symposium on VLSI Circuits.

An advanced 0.5 /spl mu/m CMOS/SOI technology for practical ultrahigh-speed and low-power circuits

Tsutomu Hirao, Koichiro Mashiko, Takashi Iwamatsu, 1995, 1995 IEEE International SOI Conference Proceedings.

A Second-Order Multibit Complex Bandpass DeltaSigmaAD Modulator with I, Q Dynamic Matching and DWA Algorithm

Toshiro Tsukada, Haruo Kobayashi, Tatsuji Matsuura, 2007, IEICE Trans. Electron..

A 4-Mbit DRAM with folded-bit-line adaptive sidewall-isolated capacitor (FASIC) cell

Yoshio Matsuda, Koichiro Mashiko, Michihiro Yamada, 1987 .

Leading-zero anticipatory logic for high-speed floating point addition

Hiroaki Suzuki, Hiroshi Makino, Koichiro Mashiko, 1995, Proceedings of the IEEE 1995 Custom Integrated Circuits Conference.

Dynamic random memory.

Kazutami Arimoto, Koichiro Mashiko, Toshifumi Kobayashi, 1984 .

Complex Bandpass DeltaSigmaAD Modulator Architecture without I, Q-Path Crossing Layout

Toshiro Tsukada, Kazuyuki Kobayashi, Haruo Kobayashi, 2006, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

3.0 Gb/s, 272 mW, 8: 1 multiplexer and 4.1 Gb/s, 388 mW, 1:8 demultiplexer

Hisayasu Sato, Koichiro Mashiko, K. Ueda, 1995 .

Substrate-bias effect and source-drain breakdown characteristics in body-tied short-channel SOI MOSFET's

T. Iwamatsu, S. Maegawa, Koichiro Mashiko, 1999 .

High-Speed SOI 1/8 Frequency Divider Using Field-Shield Body-Fixed Structure

Koichiro Mashiko, K. Ueda, Yasuo Yamaguchi, 1996 .

Feasibility of 0.18 /spl mu/m SOI CMOS technology using hybrid trench isolation with high resistivity substrate for embedded RF/analog applications

T. Iwamatsu, Koichiro Mashiko, Masahide Inuishi, 2001 .

A fully compensated active pull-down ECL circuit with self-adjusting driving capability

Koichiro Mashiko, N. Sasaki, K. Ueda, 1994, Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting.

A 286 MHz 64-b floating point multiplier with enhanced CG operation

Koichiro Mashiko, Hiroshi Makino, Y. Nakase, 1996 .

Ultra Low Power Operation of Partially-Depleted SOI/CMOS Integrated Circuits

Tsutomu Yoshimura, Koichiro Mashiko, K. Ueda, 2000 .