K. Kishine

A high-speed, low-power bipolar digital circuit for Gb/s LSI's: current mirror control logic

H. Ichino, Y. Kobayashi, K. Kishine, 1997 .

An electric power conversion system composed of two parallel-connected converters providing different output currents

K. Kishine, H. Inaba, Y. Igura, 2012, 2012 15th International Conference on Electrical Machines and Systems (ICEMS).

A 2.5-Gb/s clock and data recovery IC with tunable jitter characteristics for use in LANs and WANs

Noboru Ishihara, Haruhiko Ichino, K. Takiguchi, 1999 .

A 10G Burst-Mode PIN-TIA Module with 10-nsec Response for PON Systems

N. Yoshimoto, S. Kimura, S. Nishihara, 2007, LEOS 2007 - IEEE Lasers and Electro-Optics Society Annual Meeting Conference Proceedings.

Fast-acquisition PLL using fully digital natural-frequency-switching technique

K. Kishine, M. Harada, A. Yamagishi, 2008 .

Loop-parameter optimization of a PLL for a low-jitter 2.5-Gb/s one-chip optical receiver IC with 1: 8 DEMUX

H. Ichino, K. Kishine, K. Ishii, 2002 .