Masumi Saitoh

发表

Ag Ionic Memory Cell Technology for Terabit-Scale High-DensityApplication

Shosuke Fujii, Reika Ichihara, Takuya Konno, 2019, 2019 Symposium on VLSI Circuits.

Hot carrier degradation, TDDB, and 1/f noise in Poly-Si Tri-gate nanowire transistor

Yoko Yoshimura, Masumi Saitoh, Kensuke Ota, 2018, 2018 IEEE International Reliability Physics Symposium (IRPS).

Analysis of static noise margin improvement for low voltage SRAM composed of nano-scale MOSFETs with ideal subthreshold factor and small variability

Masumi Saitoh, Kensuke Ota, Chika Tanaka, 2015 .

Emerging nanoscale silicon devices taking advantage of nanostructure physics

Masumi Saitoh, Toshiro Hiramoto, Gen Tsutsui, 2006, IBM J. Res. Dev..

Effects of Discrete Quantum Levels on Electron Transport in Silicon Single-Electron Transistors with an Ultra-Small Quantum Dot

Masumi Saitoh, Toshiro Hiramoto, 2001 .

In-memory Reinforcement Learning with Moderately-Stochastic Conductance Switching of Ferroelectric Tunnel Junctions

Takao Marukame, Jun Deguchi, Shosuke Fujii, 2019, 2019 Symposium on VLSI Technology.

All-Optical Wavelength Conversion Using a Fabry-Perot Semiconductor Optical Amplifier

Yoshiaki Nakano, Mitsuru Takenaka, Masumi Saitoh, 2001 .

Self-align electrode separation of directionally coupled semiconductor optical amplifier

Yoshiaki Nakano, Mitsuru Takenaka, Masumi Saitoh, 2001, ITCom.

New layout design methodology for monolithically integrated 3D CMOS logic circuits based on parasitics engineering

Masumi Saitoh, Chika Tanaka, Keiji Ikeda, 2015, 2015 45th European Solid State Device Research Conference (ESSDERC).

Emerging Non-Volatile Memory and Thin-Film Transistor Technologies for Future 3D-LSI

Kiwamu Sakuma, Shosuke Fujii, Marina Yamaguchi, 2018, 2018 48th European Solid-State Device Research Conference (ESSDERC).

Impact of specific failure mechanisms on endurance improvement for HfO2-based ferroelectric tunnel junction memory

Shosuke Fujii, Reika Ichihara, Marina Yamaguchi, 2018, 2018 IEEE International Reliability Physics Symposium (IRPS).

Spice-based performance analysis of ultra-low voltage Si nanowire CMOS circuits

Masumi Saitoh, Ken Uchida, Kensuke Ota, 2011, 2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC).

Effects of oxidation process on the tunneling barrier structures in room-temperature operating silicon single-electron transistors

Masumi Saitoh, Toshiro Hiramoto, T. Hiramoto, 2002 .

Voltage gain dependence of the negative differential conductance width in silicon single-hole transistors

Masumi Saitoh, Toshiro Hiramoto, Kousuke Miyaji, 2006 .

Effects of Dot Size and its Distribution on Electron Number Control in Metal-Oxide-Semiconductor-Field-Effect-Transistor Memories Based on Silicon Nanocrystal Floating Dots

Masumi Saitoh, Toshiro Hiramoto, Takashi Inukai, 2001 .

Very Sharp Room-Temperature Negative Differential Conductance in Silicon Single-Hole Transistor with High Voltage Gain

Masumi Saitoh, Toshiro Hiramoto, Kousuke Miyaji, 2005 .

Effects of Channel Thinning on Threshold Voltage Shift in Ultrathin-Body Silicon Nanocrystal Memories

Masumi Saitoh, Toshiro Hiramoto, Kosuke Yanagidaira, 2005 .

Superior mobility characteristics in [110]-oriented ultra thin body pMOSFETs with SOI thickness less than 6 nm

Masumi Saitoh, Toshiro Hiramoto, Gen Tsutsui, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

First demonstration and performance improvement of ferroelectric HfO2-based resistive switch with low operation current and intrinsic diode property

Shosuke Fujii, Masumi Saitoh, Yasushi Nakasaki, 2016, 2016 IEEE Symposium on VLSI Technology.

Understanding of strain effects on high-field carrier velocity in (100) and (110) CMOSFETs under quasi-ballistic transport

Masumi Saitoh, Ken Uchida, T. Numata, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

Investigation of Switching-Induced Local Defects in Oxide-Based CBRAM Using Expanded Analytical Model of TDDB

Shosuke Fujii, Reika Ichihara, Marina Yamaguchi, 2019, IEEE Transactions on Electron Devices.

Large Electron Addition Energy above 250 meV in a Silicon Quantum Dot in a Single-Electron Transistor

Masumi Saitoh, Toshiro Hiramoto, Nobuyoshi Takahashi, 2001 .

Low-power linear computation using nonlinear ferroelectric tunnel junction memristors

Shosuke Fujii, Marina Yamaguchi, Masumi Saitoh, 2020, Nature Electronics.

Systematic understanding of channel-size dependence of low-frequency noise in 10nm-diameter tri-gate nanowire MOSFETs

Masumi Saitoh, Kensuke Ota, Chika Tanaka, 2013, 2013 Symposium on VLSI Technology.

Source/drain and gate engineering on Si nanowire transistors with reduced parasitic resistance and strained silicon channel

Masumi Saitoh, Ken Uchida, Kensuke Ota, 2010, 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology.

Design methodology of tri-gate poly-Si MOSFETs with 10nm nanowire channel to enhance short-channel performance and reduce Vth & Id variability

Masumi Saitoh, Kensuke Ota, Chika Tanaka, 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

Room-Temperature Observation of Negative Differential Conductance Due to Large Quantum Level Spacing in Silicon Single-Electron Transistor

Masumi Saitoh, Toshiro Hiramoto, 2004 .

Experimental Study of Random Telegraph Noise in Trigate Nanowire MOSFETs

Masumi Saitoh, Kensuke Ota, Chika Tanaka, 2015, IEEE Transactions on Electron Devices.

Carrier transport analysis of high-performance poly-Si Nanowire transistor fabricated by advanced SPC with record-high electron mobility

Kiwamu Sakuma, Masumi Saitoh, Minoru Oda, 2015, 2015 IEEE International Electron Devices Meeting (IEDM).

Experimental study of time-dependent dielectric breakdown in tri-gate nanowire transistor

Masumi Saitoh, Kensuke Ota, Chika Tanaka, 2016 .

Extension of Coulomb blockade region by quantum confinement in the ultrasmall silicon dot in a single-hole transistor at room temperature

Masumi Saitoh, Toshiro Hiramoto, T. Hiramoto, 2004 .

Ag Ionic Memory Cell Technology for Terabit-Scale High-Density Application

Shosuke Fujii, Reika Ichihara, Takuya Konno, 2019, 2019 Symposium on VLSI Technology.

Analysis of Read Margin Improvement for Low Voltage SRAM Composed of Nano-Scale MOSFETs with Ideal Subthreshold Factor and Small Variability

Masumi Saitoh, Kensuke Ota, Toshinori Numata, 2012 .

Carrier transport and stress engineering in advanced nanoscale MOS transistors

Masumi Saitoh, Ken Uchida, 2009, 2009 International Symposium on VLSI Technology, Systems, and Applications.

Transport spectroscopy of the ultrasmall silicon quantum dot in a single-electron transistor

Masumi Saitoh, Toshiro Hiramoto, Takashi Inukai, 2001 .

Room-temperature demonstration of highly-functional single-hole transistor logic based on quantum mechanical effect

Masumi Saitoh, Toshiro Hiramoto, T. Hiramoto, 2004 .

Room-Temperature Operation of Current Switching Circuit Using Integrated Silicon Single-Hole Transistors

Masumi Saitoh, Toshiro Hiramoto, T. Hiramoto, 2005 .