Yongping Han

24.8 A 14nm fractional-N digital PLL with 0.14psrms jitter and −78dBc fractional spur for cellular RFICs

Sangwook Han, Shinwoong Kim, Chulho Kim, 2017, 2017 IEEE International Solid-State Circuits Conference (ISSCC).

A 28-nm 75-fsrms Analog Fractional- $N$ Sampling PLL With a Highly Linear DTC Incorporating Background DTC Gain Calibration and Reference Clock Duty Cycle Correction

Pei-Yuan Chiang, Chih-Wei Yao, Ronghua Ni, 2019, IEEE Journal of Solid-State Circuits.

Reconfigurable Antennas and RF Front Ends for the Development of a Universal Wireless Receiver

Aly E. Fathy, Yongping Han, Vijay K. Nair, 2005 .

Towards a Universal Multi-Standard RF Receiver

Yongping Han, 2006 .

A CMOS 1.5-Bit ΣΔ Digital IF to RF Transmitter for WCDMA Application

Bertan Bakkaloglu, Yongping Han, Sayfe Kiaei, 2011 .

A 0.18μm CMOS fully integrated RFDAC and VGA for WCDMA transmitters

Yongping Han, B. Bakkaloglu, S. Kiaei, 2008, 2008 IEEE Radio Frequency Integrated Circuits Symposium.

Multi-standard wireless receiver utilizing reconfigurable antennas and RF front ends

Yongping Han, A.E. Fathy, Songnan Yang, 2006, 2006 IEEE Radio and Wireless Symposium.

A 5.5-7.3 GHz Analog Fractional-N Sampling PLL in 28-nm CMOS with 75 fsrmsJitter and −249.7 dB FoM

Pei-Yuan Chiang, Chih-Wei Yao, Ronghua Ni, 2018, 2018 IEEE Radio Frequency Integrated Circuits Symposium (RFIC).