Yongrong Zuo

24.8 A 14nm fractional-N digital PLL with 0.14psrms jitter and −78dBc fractional spur for cellular RFICs

Sangwook Han, Shinwoong Kim, Chulho Kim, 2017, 2017 IEEE International Solid-State Circuits Conference (ISSCC).

A dynamically-biased 2G/3G/4G multi-band transmitter with > 4dBm Pout, < −65dBc CIM3 and < −157dBc/Hz out-of-band noise in 28nm CMOS

Siddharth Seth, Yongrong Zuo, Sang Won Son, 2015, 2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC).

A Dynamically Biased Multiband 2G/3G/4G Cellular Transmitter in 28 nm CMOS

Siddharth Seth, Dae Hyun Kwon, Yongrong Zuo, 2016, IEEE Journal of Solid-State Circuits.

A 28-nm 75-fsrms Analog Fractional- $N$ Sampling PLL With a Highly Linear DTC Incorporating Background DTC Gain Calibration and Reference Clock Duty Cycle Correction

Pei-Yuan Chiang, Chih-Wei Yao, Ronghua Ni, 2019, IEEE Journal of Solid-State Circuits.

A 14-nm 0.14-psrms Fractional-N Digital PLL With a 0.2-ps Resolution ADC-Assisted Coarse/Fine-Conversion Chopping TDC and TDC Nonlinearity Calibration

Shinwoong Kim, Chulho Kim, Chih-Wei Yao, 2017, IEEE Journal of Solid-State Circuits.

21.6 A Sub-6GHz 5G New Radio RF Transceiver Supporting EN-DC with 3.15Gb/s DL and 1.27Gb/s UL in 14nm FinFET CMOS

Sangwook Han, Seunghyun Oh, Chih-Wei Yao, 2019, 2019 IEEE International Solid- State Circuits Conference - (ISSCC).

A Sub-6-GHz 5G New Radio RF Transceiver Supporting EN-DC With 3.15-Gb/s DL and 1.27-Gb/s UL in 14-nm FinFET CMOS

Chih-Wei Yao, Ronghua Ni, Yongrong Zuo, 2019, IEEE Journal of Solid-State Circuits.

A 5.5-7.3 GHz Analog Fractional-N Sampling PLL in 28-nm CMOS with 75 fsrmsJitter and −249.7 dB FoM

Pei-Yuan Chiang, Chih-Wei Yao, Ronghua Ni, 2018, 2018 IEEE Radio Frequency Integrated Circuits Symposium (RFIC).