Nam-Seog Kim

发表

24.8 A 14nm fractional-N digital PLL with 0.14psrms jitter and −78dBc fractional spur for cellular RFICs

Sangwook Han, Shinwoong Kim, Chulho Kim, 2017, 2017 IEEE International Solid-State Circuits Conference (ISSCC).

Programmable and automatically adjustable on-die terminator for DDR3-SRAM interface

Nam-Seog Kim, Hyun-Geun Byun, Yong-jin Yoon, 2003, Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, 2003..

A 0.2 to 1.7 GHz low-jitter integer-N QPLL for power efficient direct digital RF modulator

Jan M. Rabaey, Nam-Seog Kim, 2013, 2013 IEEE Asian Solid-State Circuits Conference (A-SSCC).

8Gb 3D DDR3 DRAM using through-silicon-via technology

So-Ra Kim, Hoon Lee, Tae-Kyung Jung, 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

A 1.04 - 4V, Digital-Intensive Dual-Mode BLE 5.0/IEEE 802.15.4 Transceiver SoC with extended range in 28nm CMOS

Shinwoong Kim, Chulho Kim, Chih-Wei Yao, 2019, 2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC).

A 3–10mW, 3.1–10.6GHz integer-N QPLL with reference spur reduction technique for UWB-based cognitive radios

Jan M. Rabaey, Nam-Seog Kim, 2015, 2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC).

Multi-mode sub-Nyquist rate digital-to-analog conversion for direct waveform synthesis

Jan M. Rabaey, Nam-Seog Kim, Stanley Yuan-Shih Chen, 2008, 2008 IEEE Workshop on Signal Processing Systems.

A High Data-Rate Energy-Efficient Triple-Channel UWB-Based Cognitive Radio

Jan M. Rabaey, Nam-Seog Kim, 2016, IEEE Journal of Solid-State Circuits.

A 10b 600MS/s multi-mode CMOS DAC for multiple Nyquist zone operation

Nam-Seog Kim, Jan Rabaey, Stanley Yuan-Shih Chen, 2011, 2011 Symposium on VLSI Circuits - Digest of Technical Papers.

A Digital-Intensive Extended-Range Dual-Mode BLE5.0 and IEEE802.15.4 Transceiver SoC

Nam-Seog Kim, Nam-Seog Kim, 2020, IEEE Transactions on Microwave Theory and Techniques.

A pseudo-differential CMOS receiver insensitive to input common mode level

Nam-Seog Kim, Hyun-Geun Byun, Uk-Rae Cho, 2005, 2005 IEEE International Symposium on Circuits and Systems.

A Dual-Resolution Wavelet-Based Energy Detection Spectrum Sensing for UWB-Based Cognitive Radios

Jan M. Rabaey, Nam-Seog Kim, J. Rabaey, 2018, IEEE Transactions on Circuits and Systems I: Regular Papers.

A 1Gb/s energy efficient triple-channel UWB-based cognitive radio

Jan M. Rabaey, Nam-Seog Kim, 2015, 2015 Symposium on VLSI Circuits (VLSI Circuits).

SMD-based internal clock generator for memory test

Nam-Seog Kim, Hyo-Chang Kim, Hyun-Guen Byun, 2005 .

A 3.1–10.6GHz wavelet-based dual-resolution spectrum sensing with harmonic rejection mixers

Jan M. Rabaey, Nam-Seog Kim, 2015, ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC).

8 Gb 3-D DDR3 DRAM Using Through-Silicon-Via Technology

Young-Hyun Jun, Dukha Park, Sooho Cha, 2009, IEEE Journal of Solid-State Circuits.

An Energy-Efficient Triple-Channel UWB-based Cognitive Radio

Nam-Seog Kim, 2014 .

A 0.46-2.1 GHz Spurious and Oscillator-Pulling Free LO Generator for Cellular NB-IoT Transmitter with 23 dBm Integrated PAs in 28nm CMOS

Nam-Seog Kim, Juyoung Han, Thomas Byunghak Cho, 2018, 2018 IEEE Asian Solid-State Circuits Conference (A-SSCC).

A 14-nm 0.14-psrms Fractional-N Digital PLL With a 0.2-ps Resolution ADC-Assisted Coarse/Fine-Conversion Chopping TDC and TDC Nonlinearity Calibration

Shinwoong Kim, Chulho Kim, Chih-Wei Yao, 2017, IEEE Journal of Solid-State Circuits.

Programmable Digital On-Chip Terminator

Suki Kim, Tae-Hyung Kim, Nam-Seog Kim, 2002 .

A Phase-Locked Loop with Reference Clock-Based Locking Time for Above-2.0Gb/s/pin DRAM Interface

Young-Hyun Jun, Jong-Woo Kim, Nam-Seog Kim, 2007 .

Impedance matching device for a termination circuit and impedance matching method thereof

Nam-Seog Kim, Uk-Rae Cho, 2001 .

A 1.2 V 1.5 Gb/s 72 Mb DDR3 SRAM

Nam-Seog Kim, Sung-Tae Kim, Kwang-Jin Lee, 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

Circuit and method for clock signal generation

Nam-Seog Kim, Yong-jin Yoon, 2002 .

Reliability challenges of through-silicon-via (TSV) stacked memory chips for 3-D integration: From transistors to packages

Nam-Seog Kim, Ho-Young Son, Woong-Sun Lee, 2013, 2013 IEEE International Interconnect Technology Conference - IITC.

Denoising Traffic Collision Data Using Ensemble Empirical Mode Decomposition and Its Application for Constructing Continuous Risk Profile

Keechoo Choi, Nam-Seog Kim, Jeong Whon Yu, 2014 .

A SRAM Core Architecture with Adaptive Cell Bias Scheme

Nam-Seog Kim, Uk-Rae Cho, Hyo-Chang Kim, 2006, 2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers..

Low voltage wide range DLL-based quad-phase core clock generator for high speed network SRAM application

Nam-Seog Kim, Hyun-Geun Byun, Uk-Rae Cho, 2005, Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005..

SIP solution for high-end multimedia cellular phone

Nam-Seog Kim, Kiwon Choi, Seung-Bae Lee, 2003 .

New dynamic logic-level converters for high performance application

Nam-Seog Kim, Yong-jin Yoon, Hyun-Geun Byun, 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

Denoising traffic collision data using ensemble empirical mode decomposition (EEMD) and its application for constructing continuous risk profile (CRP).

Keechoo Choi, Nam-Seog Kim, Jeong Whon Yu, 2014, Accident; analysis and prevention.

A knowledge based freight management decision support system incorporating economies of scale: multimodal minimum cost flow optimization approach

Byungkyu Brian Park, Nam-Seog Kim, Kang-Dae Lee, 2016, Inf. Technol. Manag..

A 3.1–10.6-GHz 57-Bands CMOS Frequency Synthesizer for UWB-Based Cognitive Radios

Jan M. Rabaey, Nam-Seog Kim, J. Rabaey, 2018, IEEE Transactions on Microwave Theory and Techniques.