Daehyeon Kwon

24.8 A 14nm fractional-N digital PLL with 0.14psrms jitter and −78dBc fractional spur for cellular RFICs

Sangwook Han, Shinwoong Kim, Chulho Kim, 2017, 2017 IEEE International Solid-State Circuits Conference (ISSCC).

A 14-nm 0.14-psrms Fractional-N Digital PLL With a 0.2-ps Resolution ADC-Assisted Coarse/Fine-Conversion Chopping TDC and TDC Nonlinearity Calibration

Shinwoong Kim, Chulho Kim, Chih-Wei Yao, 2017, IEEE Journal of Solid-State Circuits.

Digital PLL design challenges for cellular RFICs

Chih-Wei Yao, Wing Fai Loke, Ronghua Ni, 2017, 2017 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT).

Low-power programmable high-gain time difference amplifier with regeneration time control

Minjae Lee, Daehyeon Kwon, Minuk Heo, 2014 .