Mario Steinert

Power consumption optimization for low latency Viterbi Decoder

Stefano Marsili, Mario Steinert, 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

RTL processor synthesis for architecture exploration and implementation

Rainer Leupers, Gerd Ascheid, Heinrich Meyr, 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

Testability of path history memories with register-exchange architecture used in Viterbi-decoders

Mario Steinert, Stefan R. Meier, Steffen Buch, 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

Using SystemC for Hardware Design Comparison of results with VHDL , Cossap and CoCentric

Steffen Buch, David Slogsnat, Mario Steinert, 2002 .