K. Sueoka

Thermal stress and die-warpage analyses of 3D die stacks on organic substrates

S. Kohara, K. Sueoka, A. Horibe, 2012, 2012 2nd IEEE CPMT Symposium Japan.

Experimental thermal resistance evaluation of a three-dimensional (3D) chip stack, including the transient measurements

K. Sakuma, K. Sueoka, K. Matsumoto, 2012, 2012 28th Annual IEEE Semiconductor Thermal Measurement and Management Symposium (SEMI-THERM).

Thermal design guidelines for a three-dimensional (3D) chip stack, including cooling solutions

K. Sakuma, K. Sueoka, K. Matsumoto, 2013, 29th IEEE Semiconductor Thermal Measurement and Management Symposium.