Jeongseok Chae

Efficient fully-floating double-sampling integrator for DeltaSigma ADCs.

Gabor C. Temes, Kyehyung Lee, Jeongseok Chae, 2008, ISCAS 2008.

A Noise-Coupled Time-Interleaved Delta-Sigma ADC With 4.2 MHz Bandwidth, ${-}$ 98 dB THD, and 79 dB SNDR

Gabor C. Temes, Koichi Hamashita, Kaoru Takasuka, 2008, IEEE Journal of Solid-State Circuits.

A Noise-Coupled Time-Interleaved ΔΣ ADC with 4.2MHz BW, -98dB THD, and 79dB SNDR

Gabor C. Temes, Koichi Hamashita, Kaoru Takasuka, 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

Efficient fully-floating double-sampling integrator for ΔΣ ADCs

Gabor C. Temes, Kyehyung Lee, Jeongseok Chae, 2008, 2008 IEEE International Symposium on Circuits and Systems.

Low-power and low-offset comparator using latch load

Gabor C. Temes, Jeongseok Chae, Y. Jung, 2011 .

A 12-bit 7 µW/channel 1 kHz/channel incremental ADC for biosensor interface circuits

Gabor C. Temes, Patrick Chiang, Chia-Hung Chen, 2012, 2012 IEEE International Symposium on Circuits and Systems.

Efficient floating double-sampling integrator for DS ADCs

Gabor C. Temes, Jeongseok Chae, Kyehyung Lee, 2007 .

A double-sampled low-distortion cascade ΔΣ modulator with an adder/integrator for WLAN application

Pavan Kumar Hanumolu, Gabor C. Temes, Koichi Hamashita, 2011, 2011 IEEE Custom Integrated Circuits Conference (CICC).

A 63 dB 16 mW 20 MHz BW double-sampled ΔΣs analog-to-digital converter with an embedded-adder quantizer

Pavan Kumar Hanumolu, Gabor C. Temes, Koichi Hamashita, 2010, IEEE Custom Integrated Circuits Conference 2010.

A Noise-Coupled Time-Interleaved Delta-Sigma ADC with 4 . 2 MHz BW ,-98 dB THD , and 79 dB SNDR

Gabor C. Temes, Koichi Hamashita, Kaoru Takasuka, 2008 .