D.W. Bailey

Fast algorithm for clock grid simulation

A. Chandrakasan, P. Sotiriadis, O. Franza, 2002, Proceedings of the 28th European Solid-State Circuits Conference.

A 600 MHz superscalar RISC microprocessor with out-of-order execution

T.H. Lee, V. Peng, B.J. Benschneider, 1997, 1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers.

Design of an 8-wide superscalar RISC microprocessor with simultaneous multithreading

P. Gronowski, D.W. Bailey, M.K. Gowan, 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

The design and analysis of the clock distribution network for a 1.2 GHz Alpha microprocessor

T. Xanthopoulos, D.W. Bailey, M.K. Gowan, 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).