Frank K. Gürkaynak

发表

Near-Threshold RISC-V Core With DSP Extensions for Scalable IoT Endpoint Devices

Luca Benini, Davide Rossi, Igor Loi, 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

193 MOPS/mW @ 162 MOPS, 0.32V to 1.15V voltage range multi-core accelerator for energy efficient parallel and sequential digital processing

Luca Benini, Fabien Clermidy, Davide Rossi, 2016, 2016 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS XIX).

Variable delay ripple carry adder with carry chain interrupt detection

Andreas Peter Burg, Wolfgang Fichtner, Hubert Kaeslin, 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

Investigating the Potential of Custom Instruction Set Extensions for SHA-3 Candidates on a 16-bit Microcontroller Architecture

Andreas Peter Burg, Frank K. Gürkaynak, Jeremy Constantin, 2012, IACR Cryptol. ePrint Arch..

Field Programmable Compressor Trees: Acceleration of Multi-Input Addition on FPGAs

Paolo Ienne, Philip Brisk, Alessandro Cevrero, 2009, TRETS.

A Complete Real-Time Feature Extraction and Matching System Based on Semantic Kernels Binarized

Luca Benini, Aljoscha Smolic, Hubert Kaeslin, 2013, VLSI-SoC.

Spatially-Varying Image Warping: Evaluations and VLSI Implementations

Aljoscha Smolic, Danny Luu, Michael Schaffner, 2012, VLSI-SoC.

XwattPilot: A Full-stack Cloud System Enabling Agile Development of Transprecision Software for Low-power SoCs

Luca Benini, Christoph Hagleitner, Florian Scheidegger, 2020, 2020 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS).

DRAM or no-DRAM? Exploring linear solver architectures for image domain warping in 28 nm CMOS

Luca Benini, Aljoscha Smolic, Michael Schaffner, 2015, 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Leakage Bounds for Gaussian Side Channels

Luca Benini, Thomas Unterluggauer, Stefan Mangard, 2017, CARDIS.

A novel CMOS standard cell structure for self-routed clock net generation

Yusuf Leblebici, Frank K. Gürkaynak, 1999 .

GALS system design: side channel attack secure cryptographic accelerators

Frank K. Gürkaynak, 2006 .

Accuracy and Performance Trade-Offs of Logarithmic Number Units in Multi-Core Clusters

Luca Benini, Michael Schaffner, Michael Gautschi, 2016, 2016 IEEE 23nd Symposium on Computer Arithmetic (ARITH).

High speed ASIC implementations of leakage-resilient cryptography

Luca Benini, Thomas Unterluggauer, Stefan Mangard, 2018, 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Evaluating Resistance of MCML Technology to Power Analysis Attacks Using a Simulation-Based Methodology

Yusuf Leblebici, Paolo Ienne, Christof Paar, 2009, Trans. Comput. Sci..

Automatic multiview synthesis — Prototype demo

Luca Benini, Aljoscha Smolic, Hubert Kaeslin, 2015, 2015 Visual Communications and Image Processing (VCIP).

Hybrid ASIC/FPGA System for Fully Automatic Stereo-to-Multiview Conversion Using IDW

Luca Benini, Aljoscha Smolic, Hubert Kaeslin, 2016, IEEE Transactions on Circuits and Systems for Video Technology.

A current sensing completion detection method for asynchronous pipelines operating in the sub-threshold regime

Yusuf Leblebici, Frank K. Gürkaynak, Omer Can Akgun, 2009 .

Realization of a programmable rank-order filter architecture using capacitive threshold logic gates

Yusuf Leblebici, Frank K. Gürkaynak, Ilhan Hatirnaz, 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).

A 90nm CMOS cryptographic core with improved fault-tolerance in presence of massive defect density

Yusuf Leblebici, Alexandre Schmid, Maria Gabrani, 2007, Nano-Net.

Multi-core data analytics SoC with a flexible 1.76 Gbit/s AES-XTS cryptographic accelerator in 65 nm CMOS

Luca Benini, Stefan Mangard, Francesco Conti, 2017, CS2@HiPEAC.

Design and realization of a fault-tolerant 90nm CMOS cryptographic engine capable of performing under massive defect density

Yusuf Leblebici, Alexandre Schmid, Maria Gabrani, 2007, GLSVLSI '07.

High-efficiency logarithmic number unit design based on an improved cotransformation scheme

Luca Benini, Florian Scheidegger, Michael Schaffner, 2016, 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE).

4.6 A 65nm CMOS 6.4-to-29.2pJ/FLOP@0.8V shared logarithmic floating point unit for acceleration of nonlinear function kernels in a tightly coupled processor cluster

Luca Benini, Michael Schaffner, Michael Gautschi, 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).

2Gbit/s Hardware Realizations of RIJNDAEL and SERPENT: A Comparative Analysis

Wolfgang Fichtner, Hubert Kaeslin, Frank K. Gürkaynak, 2002, CHES.

Self-timed ring for globally-asynchronous locally-synchronous systems

Wolfgang Fichtner, Hubert Kaeslin, Frank K. Gürkaynak, 2003, Ninth International Symposium on Asynchronous Circuits and Systems, 2003. Proceedings..

A Modular and Scalable Architecture for the Realization of High-speed Programmable Rank Order Filters Using Threshold Logic

Yusuf Leblebici, Frank K. Gürkaynak, Ilhan Hatirnaz, 2000, VLSI Design.

Improving the power-delay product in SCL circuits using source follower output stage

Elizabeth J. Brauer, Massimo Alioto, Yusuf Leblebici, 2008, 2008 IEEE International Symposium on Circuits and Systems.

Dynamic memory-based physically unclonable function for the generation of unique identifiers and true random numbers

Hubert Kaeslin, Norbert Felber, Frank K. Gürkaynak, 2014, 2014 IEEE International Symposium on Circuits and Systems (ISCAS).

Design space exploration for field programmable compressor trees

Paolo Ienne, Philip Brisk, Alessandro Cevrero, 2008, CASES '08.

Higher radix Kogge-Stone parallel prefix adder architectures

Yusuf Leblebici, Frank K. Gürkaynak, Laurent Chaouat, 2000, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353).

An 826 MOPS, 210uW/MHz Unum ALU in 65 nm

Luca Benini, Qiuting Huang, Frank K. Gürkaynak, 2017, 2018 IEEE International Symposium on Circuits and Systems (ISCAS).

FPGA-Based High-Speed Authenticated Encryption System

Norbert Felber, Frank K. Gürkaynak, Michael Muehlberghuber, 2012, VLSI-SoC.

GALS for Bursty Data Transfer based on Clock Coupling

Xin Fan, Eckhard Grass, Milos Krstic, 2009, Electron. Notes Theor. Comput. Sci..

Breaking ECC2K-130

Tanja Lange, Peter Schwabe, Tim Güneysu, 2009, IACR Cryptol. ePrint Arch..

The Certicom Challenges ECC2-X

Tanja Lange, Peter Schwabe, Tim Güneysu, 2009, IACR Cryptol. ePrint Arch..

Approximate 32-bit floating-point unit design with 53% power-area product reduction

Christian Enz, Michael Gautschi, Frank K. Gürkaynak, 2016, ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference.

An Extended Shared Logarithmic Unit for Nonlinear Function Kernel Acceleration in a 65-nm CMOS Multicore Cluster

Luca Benini, Michael Schaffner, Michael Gautschi, 2017, IEEE Journal of Solid-State Circuits.

Instruction Set Extensions for Cryptographic Hash Functions on a Microcontroller Architecture

Andreas Peter Burg, Frank K. Gürkaynak, Jeremy Constantin, 2012, 2012 IEEE 23rd International Conference on Application-Specific Systems, Architectures and Processors.

A current sensing completion detection method for asynchronous pipelines operating in the sub-threshold regime

Yusuf Leblebici, Frank K. Gürkaynak, Omer Can Akgun, 2009, Int. J. Circuit Theory Appl..

Efficient and side-channel-aware implementations of elliptic curve cryptosystems over prime fields

Yusuf Leblebici, Berk Sunar, Frank K. Gürkaynak, 2010, IET Inf. Secur..

Prevention of Microarchitectural Covert Channels on an Open-Source 64-bit RISC-V Core pdf

Luca Benini, Frank K. Gürkaynak, Moritz Schneider, 2020, ArXiv.

A compact modular architecture for the realization of high-speed binary sorting engines based on rank ordering

Yusuf Leblebici, Frank K. Gürkaynak, Ilhan Hatirnaz, 2000, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353).

Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs

Paolo Ienne, Philip Brisk, Alessandro Cevrero, 2008, FPGA '08.

A compact modular architecture for high-speed binary sorting

Yusuf Leblebici, Frank K. Gürkaynak, Ilhan Hatirnaz, 2000, 2000 IEEE International Conference on Acoustics, Speech, and Signal Processing. Proceedings (Cat. No.00CH37100).

A general-transformation EWA view rendering engine for 1080p video in 130 nm CMOS

Michael Schaffner, Frank K. Gürkaynak, Pierre Greisen, 2012, 2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC).

Globally Asynchronous, Locally Synchronous Circuits: Overview and Outlook

Eckhard Grass, Milos Krstic, Pascal Vivet, 2007, IEEE Design & Test of Computers.

Developing a Hardware Evaluation Method for SHA-3 Candidates

Luca Henzen, Frank K. Gürkaynak, Patrice Guillet, 2010, CHES.

A Scalable Near-Memory Architecture for Training Deep Neural Networks on Large In-Memory Datasets

Luca Benini, Fabian Schuiki, Michael Schaffner, 2018, IEEE Transactions on Computers.

Aries: A compact modular macro-block for digital filtering applications

Yusuf Leblebici, Frank K. Gürkaynak, 1999 .

Arnold: An eFPGA-Augmented RISC-V SoC for Flexible and Low-Power IoT End Nodes pdf

Luca Benini, Pasquale Davide Schiavone, Frank K. Gürkaynak, 2020, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A 2 Gb/s balanced AES crypto-chip implementation

Andreas Peter Burg, Wolfgang Fichtner, Hubert Kaeslin, 2004, GLSVLSI '04.

Design Challenges for a Differential-Power-Analysis Aware GALS-based AES Crypto ASIC

Wolfgang Fichtner, Hubert Kaeslin, Norbert Felber, 2006, Electron. Notes Theor. Comput. Sci..

A Generic Standard Cell Design Methodology for Differential Circuit Styles

Stéphane Badel, Yusuf Leblebici, Frank K. Gürkaynak, 2008, 2008 Design, Automation and Test in Europe.

Red team vs. blue team hardware trojan analysis: detection of a hardware trojan on an actual ASIC

Frank K. Gürkaynak, Michael Hutter, Thomas Korak, 2013, HASP '13.

A Functional Test Methodology for Globally-Asynchronous Locally-Synchronous Systems

Wolfgang Fichtner, Hubert Kaeslin, Norbert Felber, 2002, ASYNC.

KISS PULPino - Updates on PULPino

Michael Gautschi, Antonio Pullini, Eric Flamand, 2016 .

Novel Front-End Circuit Architectures for Integrated Bio-Electronic Interfaces

Yusuf Leblebici, Alexandre Schmid, Frank K. Gürkaynak, 2008, 2008 Design, Automation and Test in Europe.

A real-time 720p feature extraction core based on Semantic Kernels Binarized

Hubert Kaeslin, Lukas Cavigelli, Michael Schaffner, 2013, 2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC).

Energy-Efficient Near-Threshold Parallel Computing: The PULPv2 Cluster

Luca Benini, Fabien Clermidy, Davide Rossi, 2017, IEEE Micro.

A scalable architecture for realization of compact programmable rank-order filters

Yusuf Leblebici, Frank K. Gürkaynak, I. Hatirnaz, 1999 .

Automatic multiview synthesis — Towards a mobile system on a chip

Luca Benini, Aljoscha Smolic, Hubert Kaeslin, 2015, 2015 Visual Communications and Image Processing (VCIP).

Power-analysis attack on an ASIC AES implementation

Bart Preneel, Elisabeth Oswald, Frank K. Gürkaynak, 2004, International Conference on Information Technology: Coding and Computing, 2004. Proceedings. ITCC 2004..

An approximate computing technique for reducing the complexity of a direct-solver for sparse linear systems in real-time video processing

Luca Benini, Aljoscha Smolic, Hubert Kaeslin, 2014, 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC).

GALS at ETH Zurich: success or failure?

Wolfgang Fichtner, Hubert Kaeslin, Norbert Felber, 2006, 12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'06).

A 10-core SoC with 20 Fine-Grain Power Domains for Energy-Proportional Data-Parallel Processing over a Wide Voltage and Temperature Range

Luca Benini, Fabian Schuiki, Florian Zaruba, 2021, ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC).

Security, Reliability and Test Aspects of the RISC-V Ecosystem

Matthias Sauer, Helena Handschuh, Jaume Abella, 2021, 2021 IEEE European Test Symposium (ETS).

Microarchitectural Timing Channels and their Prevention on an Open-Source 64-bit RISC-V Core

Luca Benini, Gernot Heiser, Frank K. Gürkaynak, 2021, 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE).

An IoT Endpoint System-on-Chip for Secure and Energy-Efficient Near-Sensor Analytics

Luca Benini, Davide Rossi, Stefan Mangard, 2016, IEEE Transactions on Circuits and Systems I: Regular Papers.

Hardware Evaluation of Estream Candidates

Wolfgang Fichtner, Hubert Kaeslin, Norbert Felber, 2006 .

Editorial Advisory Board Interface Layering Phenomena in Capacitance Detection of Dna with Biochips a Simple and Sensitive Flow Injection Optical Fibre Biosensor Based on Immobilised Enzyme for Monitoring of Pesticides Design and Characterization of a Solid-state Piezoelectric Transducer Chemical Se

Clive, Asif, Frank K. Gürkaynak, 2007 .

Design flow for a 3-million transistor GALS test chip

Wolfgang Fichtner, Hubert Kaeslin, Norbert Felber, 2002 .

Lessons Learned from Designing a 65 nm ASIC for Evaluating Third Round SHA-3 Candidates

Kris Gaj, Hubert Kaeslin, Frank K. Gürkaynak, 2012 .

Recommendations for Hardware Evaluation of Cryptographic Algorithms

Frank K. Gürkaynak, 2006 .

Is there hope for GALS in the future ?

Wolfgang Fichtner, Hubert Kaeslin, Norbert Felber, .

Breaking ECC 2 K-130

Frank K. Gürkaynak, Joppe W. Bos, C. Paar, 2017 .

A near-threshold RISC-V core with DSP extensions for scalable IoT Endpoint Devices

Pasquale Davide Schiavone, Frank K. Gürkaynak, L. Benini, 2016, ArXiv.

A 60 GOPS/W, −1.8 V to 0.9 V body bias ULP cluster in 28 nm UTBB FD-SOI technology

Luca Benini, Andrea Bartolini, Philippe Flatresse, 2016 .

MADmax: A 1080p stereo-to-multiview rendering ASIC in 65 nm CMOS based on image domain warping

Aljoscha Smolic, Hubert Kaeslin, Michael Schaffner, 2013, 2013 Proceedings of the ESSCIRC (ESSCIRC).