Peter Hailes

1.5 Gbit/s FPGA Implementation of a Fully-Parallel Turbo Decoder Designed for Mission-Critical Machine-Type Communication Applications

Lajos Hanzo, Robert G. Maunder, Bashir M. Al-Hashimi, 2016, IEEE Access.

A Flexible FPGA-Based Quasi-Cyclic LDPC Decoder

Lajos Hanzo, Robert G. Maunder, Bashir M. Al-Hashimi, 2017, IEEE Access.

A Survey of FPGA-Based LDPC Decoders

Robert G. Maunder, Bashir M. Al-Hashimi, Lajos Hanzo, 2016, IEEE Communications Surveys & Tutorials.

Design and implementation of flexible FPGA-based LDPC decoders

Peter Hailes, 2018 .

Research data for "A Flexible FPGA-Based Quasi-Cyclic LDPC Decoder"

Robert G. Maunder, Lajos Hanzo, Bashir M. Al-Hashimi, 2017 .

Dataset for "Hardware-Efficient Node Processing Unit Architectures for Flexible LDPC Decoder Implementations"

Lajos Hanzo, Robert G. Maunder, Peter Hailes, 2017 .

Hardware-Efficient Node Processing Unit Architectures for Flexible LDPC Decoder Implementations

Lajos Hanzo, Robert G. Maunder, Lei Xu, 2018, IEEE Transactions on Circuits and Systems II: Express Briefs.

Survey of Turbo, LDPC, and Polar Decoder ASIC Implementations

Lajos Hanzo, Robert G. Maunder, Bashir M. Al-Hashimi, 2019, IEEE Communications Surveys & Tutorials.